Threshold logic with improved signal-to-noise ratio

Details Threshold logic with improved signal-to-noise ratio Threshold logic with improved signal-to-noise ratio

1998-08-06

2000-06-20

Tokar, Michael

Electronic digital logic circuitry

Threshold

With field-effect transistor

326 35, 326 36, 326112, 326119, 706 26, 706 33, 706 41, 706 42, 706 43, H03K 1923, H03K 19094

Patent

active

060781904

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

Logic functions can be realized for example by transistor-transistor logic (TTL), by emitter-coupled logic (ECL), by complementary MOS logic (CMOS), as well as by so-called threshold value logic with neuron MOS transistors. Threshold value logic modules can be used to realize not only simple logic combinations, but also, for example, full adders, multipliers and more complex units. Essential advantages of threshold value logic primarily reside in the small number of transistors required and in the comparatively high operating speed. The susceptibility to interference is usually greater in the case of known threshold value logic circuits than in the case of other known types of logic.
The international patent application WO 95/35548 discloses, in particular in FIGS. 21 and 22, a circuit having a weighting circuit, which supplies two complementary output signals, having a first and a second circuit path, which each contain a neuron transistor for the indirect connection of a respective comparison terminal to reference-ground potential, and having neuron transistors to whose gates inverse input signals are applied.
A weighting circuit is disclosed in U.S. Pat. No. 4,843,264, for example.
The object of the invention, then, is to specify a threshold value logic circuit whose signal-to-noise ratio is improved relative to conventional threshold value logic circuits.
In general terms the present invention is a threshold value logic circuit, that comprises a weighting subcircuit for the forming a carry; a second weighting subcircuit for forming of a summation signal; a non-inverting circuit path having a first neuron transistor and a second neuron transistor and an inverting circuit path having a further first neuron transistor and a further second neuron transistor; a weighting terminal of the first weighting subcircuit for forming the carry connected to reference-ground potential via the first neuron transistor and a comparison terminal of the first weighting subcircuit connected to reference-ground potential via the further first transistor; a weighting terminal of the second weighting subcircuit for forming of the summation signal connected to reference-ground potential via the second neuron transistor and a comparison terminal of the second weighting subcircuit for forming the summation signal connected to reference-ground potential via the further second neuron transistor; a first gate of the first neuron transistor connected to a multiplicand, a second gate of the first neuron transistor connected to a multiplication factor, a third gate of the first neuron transistor connected to a carry signal of a preceding stage, a fourth gate of the first neuron transistor connected to a summation signal of the preceding stage and a fifth gate of the first neuron transistor connected to reference-ground potential; a first gate of the second neuron transistor connected to an inverted carry signal, a second gate of the neuron transistor connected to the multiplicand, a third gate of the second neuron transistor connected to the multiplication factor, a fourth gate of the second neuron transistor connected to the carry signal of the preceding stage, a fifth gate of the second neuron transistor connected to the summation signal of the preceding stage and a sixth gate of the second neuron transistor connected to reference-ground potential; gates of the further first and further second neuron transistors being supplied with signals, which are inverse of signals present at corresponding gates of the first and second neuron transistors; second p-channel MOS transistors and first, second and third n-channel MOS transistors, the first and second p-channel transistors and the first and second n-channel transistors, respectively forming first and second inverter stages, a respective output of one inverter stage of the first and second inverter stage being fed back to a respective input of the other inverter stage of the first and second inverter stages, and wherein gates of the first and second n-channe

REFERENCES:
patent: 4843264 (1989-06-01), Galbraith
patent: 5331215 (1994-07-01), Allen et al.
patent: 5469085 (1995-11-01), Shibata et al.
patent: 5594372 (1997-01-01), Shibata et al.
patent: 5608340 (1997-03-01), Shibata et al.
patent: 5661421 (1997-08-01), Ohmi et al.

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