Electronic digital logic circuitry – Threshold – With field-effect transistor
Patent
1997-10-29
1999-11-16
Santamauro, Jon
Electronic digital logic circuitry
Threshold
With field-effect transistor
326 53, H03K 1923
Patent
active
059864648
ABSTRACT:
A threshold logic circuit with a low space requirement includes a first and at least one second circuit portion, each of which has an evaluator circuit and at least two branches to be evaluated. A partial sum signal formed in the first circuit portion is jointly used for the at least one second circuit portion and is not formed separately in each case. The main advantage is a low chip area consumption.
REFERENCES:
patent: 4663740 (1987-05-01), Ebel
Abstract of International Publication No. 96/42051 (Prange), dated Dec. 27, 1996.
Abstract of International Publication No. 96/42048 (Prange et al.), dated Dec. 27, 1996.
"Some Improvements in the Implementation of Multithreshold and Multivalued I.sup.2 L circuits" (Pelayo et al.), International Journal of Electronics, vol. 66, No. 1, 1989, pp. 19-34.
"A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations" (Shibata et al.), IEEE Transactions on Electron Devices, vol. 39, No. 6, Jun. 1992, pp. 1444-1455.
Luck Andreas
Thewes Roland
Weber Werner
Greenberg Laurence A.
Le Don Phu
Lerner Herbert L.
Santamauro Jon
Siemens Aktiengesellschaft
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