Three-transistor type DRAM with a refresh circuit

Details Three-transistor type DRAM with a refresh circuit Three-transistor type DRAM with a refresh circuit

1998-05-22

1999-11-30

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Data refresh

365150, G11C 700

Patent

active

059954337

ABSTRACT:
A three-transistor type dynamic random access memory (DRAM) with a refresh circuit is disclosed. The memory includes a memory array including memory cells (40), each of the memory cells having a storing transistor (M2) used for storing a data therein; a writing transistor (M1) responsive to a signal on a write word line for transferring a signal on a write bit line to the storing transistor; and a reading transistor (M3) responsive to a signal on a read word line for transferring the data in the storing transistor to a read bit line. The memory according to the present invention also includes a refresh circuit (50) configured to latch a signal on the read bit line, the latched signal then being coupled to the write bit line when the refresh circuit is activated.

REFERENCES:
patent: 4044342 (1977-08-01), Suzuki et al.
patent: 4935896 (1990-06-01), Matsumura et al.
patent: 5262988 (1993-11-01), Ochii
patent: 5414657 (1995-05-01), Okimura
patent: 5812476 (1998-09-01), Segawa

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