Three-transistor static storage cell

Details Three-transistor static storage cell Three-transistor static storage cell

1997-04-28

1998-11-17

Nelms, David C.

Static information storage and retrieval

Systems using particular element

Flip-flop

365154, G11C 1100

Patent

active

058386068

ABSTRACT:
A SRAM storage cell has a NMOS transistor and a PMOS transistor connected with each other between a source of potential and ground. The sources, gates and gate back plates of the transistors are commonly connected and coupled to a storage node. The drain of the NMOS transistor is supplied with the potential, whereas the drain of the PMOS transistor is grounded. A pass NMOS transistor is connected between the storage node and bit and word lines. This storage cell configuration provides considerably reduced area compared to conventional static storage cells.

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