Three transistor SRAM

Details Three transistor SRAM Three transistor SRAM

2003-04-16

2004-03-16

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000

Reexamination Certificate

active

06707709

ABSTRACT:

BACKGROUND OF THE INVENTION
a. Field of the Invention
The present invention pertains to computer memory devices and specifically to static random access memory devices.
b. Description of the Background
Random access memory devices exist in many variations. Static random access memory (‘SRAM’) devices are a class of memory devices that require a constant power source so that the devices maintain the memory. Such devices are used in discrete packages or may be incorporated into integrated circuit devices that may, for example, include processors or other functionality.
A common SRAM device known in the art is comprised of six transistors. In addition to power supplies and ground connections, four control lines are required to operate the six transistor device.
One limitation of the common six transistor design are that the six transistors occupy a certain amount of area within an integrated circuit or other package.
Another limitation is that four control lines are required to operate the device. Each control line is a mechanism whereby noise or other problems may be introduced into the circuit.
It may therefore be advantageous to provide an SRAM device that has a smaller footprint than existing SRAM devices. It would further be advantageous to provide an SRAM device that eliminates one or more of the control lines necessary to operate the device.
SUMMARY OF THE INVENTION
The present invention overcomes the disadvantages and limitations of the prior art by providing a system and method for a static random access memory that is comprised of three transistors and two resistors. The transistors and resistors are connected to a voltage source VDD, ground VCC, a word line WL, a bit line BL, and a second bit line BLB. Operating WL, BL, and BLB in specific sequences controls the device. Further, the state of the device may be queried by raising the WL line and reading the state on the BL line.
The present invention may therefore comprise a static random access memory device comprising: a first transistor having a drain, a gate, and a source; a second transistor having a drain connected to the gate of the first transistor and a gate connected to the drain of the first transistor; a ground signal connected to the source of the first transistor and the source of the second transistor; a third transistor having a drain, a gate, and a source, the drain of the third transistor connected to the drain of the first transistor, a first resistor having a first connection and a second connection, the first connection of the first resistor being connected to the drain of the first transistor; a second resistor having a first connection and a second connection, the first connection of the second resistor being connected to the drain of the second transistor; a first power supply being connected to the second connection of the first resistor and the second connection of the second resistor; a second power supply being connected to the source of the third transistor; a first signal line connected to the gate of the third transistor; a second signal line connected to the second connection of the first resistor; and a third signal line connected to the source of the third transistor.
The present invention may further comprise a method of manufacturing a static random access memory device comprising: providing a first transistor having a drain, a gate, and a source; providing a second transistor having a drain, a gate, and a source; connecting the drain of the second transistor to the gate of the first transistor; connecting the drain of the first transistor to the gate of the second transistor, providing a ground signal; connecting the ground signal to the source of the first transistor and the source of the second transistor; providing a third transistor having a drain, a gate, and a source; connecting the drain of the third transistor to the drain of the first transistor; providing a first resistor having a first connection and a second connection; connecting the first connection of the first resistor to the drain of the first transistor; providing a second resistor having a first connection and a second connection; connecting the first connection of the second resistor to the drain of the second transistor, providing a first power supply; connecting the second connection of the first resistor and the second connection of the second resistor to the first power supply; providing a second power supply, connecting the source of the third transistor to the second power supply; providing a first signal line; connecting the first signal line to the gate of the third transistor; providing a second signal line; connecting the second signal line to the second connection of the first resistor; providing a third signal line; and connecting the third signal line to the source of the third transistor.
The advantages of the present invention are that fewer transistor devices are required to create an SRAM cell, leading to a reduced footprint for the equivalent functionality of other designs. Further, a reduction in the number of control wires results in the present invention being less susceptible to noise and other interference.


REFERENCES:
patent: 6205049 (2001-03-01), Lien et al.

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