Three transistor multi-state dynamic memory cell for embedded CM

Details Three transistor multi-state dynamic memory cell for embedded CM Three transistor multi-state dynamic memory cell for embedded CM

1998-02-05

2000-01-18

Nelms, David

Static information storage and retrieval

Systems using particular element

Capacitors

365187, G11C 1124

Patent

active

060162686

ABSTRACT:
Methods are disclosed in making a multi-state dynamic memory using a three transistor cell. The cell construction is consistent with a logic semiconductor process and is therefore useful for embedded memory applications. Considerations are given to write levels, read levels, reference devices, and sense amplifier design. Two cell enhancements are proposed: substituting a PFET in place of and NFET for the write select transistor so that improved noise margin can be achieved and adding a capacitor for extended refresh times. Methods are also introduced to reduce select transistor leakage current during the deselected state.

REFERENCES:
patent: 4803664 (1989-02-01), Itoh
patent: 4935896 (1990-06-01), Matsumura et al.
patent: 4989055 (1991-01-01), Redwine
patent: 5283761 (1994-02-01), Gillingham
patent: 5652728 (1997-07-01), Hosotani et al.
patent: 5812476 (1998-09-01), Segawa

Affiliated with

Also associated with

Rating

Three transistor multi-state dynamic memory cell for embedded CM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Three transistor multi-state dynamic memory cell for embedded CM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Three transistor multi-state dynamic memory cell for embedded CM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-567340