Three-tiered translation lookaside buffer hierarchy in a...

Details Three-tiered translation lookaside buffer hierarchy in a... Three-tiered translation lookaside buffer hierarchy in a...

2011-04-12

2011-04-12

Bragdon, Reginald G (Department: 2189)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S206000, C711S207000, C711S122000, C711SE12016, C711SE12061, C711S136000

Reexamination Certificate

active

07925859

ABSTRACT:
A three-tiered TLB architecture in a multithreading processor that concurrently executes multiple instruction threads is provided. A macro-TLB caches address translation information for memory pages for all the threads. A micro-TLB caches the translation information for a subset of the memory pages cached in the macro-TLB. A respective nano-TLB for each of the threads caches translation information only for the respective thread. The nano-TLBs also include replacement information to indicate which entries in the nano-TLB/micro-TLB hold recently used translation information for the respective thread. Based on the replacement information, recently used information is copied to the nano-TLB if evicted from the micro-TLB.

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