Three terminal non-volatile memory element

Details Three terminal non-volatile memory element Three terminal non-volatile memory element

2000-06-07

2001-07-24

Mai, Son (Department: 2818)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S096000, C365S187000

Reexamination Certificate

active

06266269

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile memory cell, and particularly to a three terminal memory element using a standard CMOS transistor.
2. Description of the Related Art
MOS (metal oxide semiconductor) transistors are well known in the art. An MOS transistor includes a source and a drain, formed as diffusion areas in the substrate, as well as a channel region extending between the source and drain. A gate, typically a polycrystalline silicon structure, is formed overlying the substrate. A gate oxide, formed with silicon dioxide layer, is provided between the gate and the channel region. A predetermined voltage on the gate creates the channel, which connects the source and drain. Thus, by controlling the voltage, an MOS device can be used as a switch having an ON or OFF state.
If the source and drain are N type formed in a P type substrate, then the MOS transistor is called an NMOS device. In a similar manner, if the source and drain are P type formed in a N type substrate, then the MOS transistor is called a PMOS device. A complementary metal oxide semiconductor (CMOS) integrated circuit includes both NMOS and PMOS transistors.
Static random access memory (SRAM) cells are well known, volatile memory cells fabricated using (CMOS) technology. Volatile memory cells lose their stored information when power is removed from the circuit. In this manner, SRAM cells can be easily reprogrammed to a different logic state. However, an unexpected loss of power requires reprogramming of the SRAM cells.
In contrast, non-volatile memory cells preserve their stored information even if power is removed. Moreover, many applications for integrated circuits require the security provided by non-volatile memory cells. Therefore, it would be desirable for integrated circuits to include both non-volatile and volatile memory cells, thereby providing the end user with optimal flexibility as well as security.
However, conventional, non-volatile memory cells are substantially different from those used in typical, volatile memory cells, thereby requiring different fabrication techniques. Thus, if non-volatile memory cells are included on an integrated circuit fabricated using conventional CMOS technology, then chip size and complexity are undesirably increased.
FIG. 1A
illustrates a known memory system
100
located on an integrated circuit with other circuitry (not shown). This circuitry can include, for example, circuitry relating to a field programmable gate array (FPGA). In one embodiment, memory system
100
, which includes both low voltage and high voltage transistors, is fabricated in accordance with a 0.18 &mgr;m CMOS process. The low voltage transistors are designed to operate in response to a supply voltage of 1.8 Volts, whereas the high voltage transistors are designed to operate in response to a supply voltage of 3.3 Volts.
Memory system
100
includes an illustrative 4×4 array of memory cells
101
, each memory cell
101
including a write access transistor
102
, a storage transistor
103
, and a read access transistor
104
. Storage transistors
103
are low voltage NMOS transistors having a gate oxide thickness of 40 Å, a channel width of 0.6 &mgr;m and a channel length of 0.25 &mgr;m. Write access transistors
102
are high voltage PMOS transistors having a gate oxide thickness of 70 Å, a channel width of 1 &mgr;m and a channel length of 0.6 &mgr;m. In contrast, read access transistors
104
are high voltage NMOS transistors having a gate oxide thickness of 70 Å, a channel width of 10 &mgr;m and a channel length of 0.6 &mgr;m.
Storage transistor
103
is programmed by applying a programming voltage (VPP) across its gate oxide layer, thereby rupturing this layer. When the gate oxide is ruptured, a conductive path is formed between the gate, source, and drain of the storage transistor. If the gate oxide of a storage transistor is not ruptured, then no such conductive path exists. In the embodiment of
FIG. 1
, the drain and source of the storage transistor are connected to ground. Thus, to apply the programming voltage VPP across the gate oxide layer, a programming voltage VPP is applied to the gate of storage transistor
103
.
The programming voltage VPP is applied to the gate of storage transistor
103
through write access transistor
102
. However, the breakdown voltage of write access transistor
102
is at least 1.5 Volts higher than the breakdown voltage of read access transistor
104
. In this manner, the high breakdown voltage of write access transistor
102
allows the use of a relatively high programming voltage VPP.
FIG. 1B
illustrates the breakdown characteristics of a high voltage PMOS transistor (such as write access transistor
102
), a low voltage NMOS transistor (such as storage transistor
103
), and a high voltage NMOS (such as read access transistor
104
). The breakdown characteristics of transistors
102
,
103
, and
104
are shown by lines
102
A,
103
A and
104
A, respectively.
As illustrated by line
103
A, the low voltage NMOS transistor has a breakdown voltage of about 6 Volts. However, as illustrated by line
104
A, at 6 Volts, the high voltage NMOS transistor operates in a Fowler-Nordheim tunneling region, which may harm its gate oxide. (The Fowler-Nordheim tunneling region begins at the knee of the curve in line
104
A.) Consequently, it is undesirable to use a high voltage NMOS transistor as a write access transistor.
As illustrated by line
102
A, a high voltage PMOS transistor does not begin to operate in the Fowler-Nordheim tunneling region until about 7.5 to 8 Volts. Thus, there is a safe operating margin that exists between the breakdown voltage of a low voltage NMOS transistor (such as storage transistor
103
), and the Fowler-Nordheim tunneling region of a high voltage PMOS transistor (such as write access transistor
102
). This margin enables write access transistor
102
to safely transfer the programming voltage VPP.
Referring back to
FIG. 1A
, the memory cells in each row are coupled to a common write word line (WWL) and a common read word line (RWL). Similarly, the memory cells in each column are coupled to the common read bit line (RBL) and a common write bit line (WBL). Word line control circuit
120
generates the read and write enable signals to be applied to read word lines RWL and write word lines WWL, respectively. Bit line control circuit
130
generates the program signals to be applied to write bit lines WBL and the read enable signals REN. Detailed descriptions of word line control circuit
120
and bit line control circuit
130
are provided in U.S. patent application, Ser. No. 09/263,375, filed on Mar. 5, 1999, which is incorporated by reference herein.
Write Operation
To program a specific memory cell
101
, word line control circuit
120
asserts a supply voltage VCC on the write word line WWL of the addressed row. Bit line control circuit
130
then asserts the programming voltage VPP on the write bit line (WBL) of the addressed column. Under these conditions, write access transistor
102
turns on, thereby applying the programming voltage VPP to the gate of storage transistor
103
. Under these conditions, the gate oxide of storage transistor
103
is ruptured, thereby programming that memory cell.
Word line control circuit
120
further applies the VCC supply voltage to all read word lines RWL. Thus, the gate-to-drain voltage of read access transistor
104
in the programmed memory cell is limited to a voltage that does not exceed the programming voltage VPP minus the VCC supply voltage. Note that this voltage is only applied until the programming operation is complete (i.e., the gate oxide is ruptured). At this time, the gate-to-drain voltage is approximately VCC. Consequently, the gate oxide of read access transistor
104
in the programmed cell is not damaged during a programming operation.
Bit line control circuit
130
provides the VCC supply voltage to all of the write bit lines WBL in the non-addressed columns. As a result, excep

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