Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2000-06-30
2001-07-31
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S063000, C326S083000
Reexamination Certificate
active
06268744
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to devices that may use a number of different voltage supply levels, and more particularly to systems and methods for allowing input/output buffers to suitably operate using different voltage supply levels.
BACKGROUND OF THE INVENTION
Graphics controller chips, like many integrated circuit devices, utilize CMOS, logic cores, and associated input/output (I/O) pads as part of their circuit makeup. I/O pads include, for example, input/output buffers coupled to a common pad or pin. There is a constant challenge to continuously design smaller, faster and more complicated integrated circuits to provide increased functionality for multimedia applications and other applications. Typically, the logic core operates at a different supply voltage than the I/O pads. For example, with logic cores having minimum gate lengths of 0.25 um and gate oxide thicknesses of 50 angstroms, a core logic supply voltage may be 2.5 volts. Corresponding supply voltages for the input/output pads, however, may be different supply voltages such as 3.3 volts. However, future generation chips require faster speeds and lower power consumption, hence, lower supply voltages so that the I/O pads can switch at faster frequencies.
Also, integrated circuits must often provide compatibility with older versions of interface circuits. As a result, an integrated circuit may require that the I/O pads operate at either a 3.3 volt level, or for example, at a lower 1.5 volt level. The gate length and gate oxide thickness of I/O pad transistors must also typically be decreased to provide faster circuits that draw less current. With multilevel supply voltages, multi-gate oxide thickness devices are often used to provide the requisite logic levels and overvoltage protection. However, a problem arises when multi-gate oxide transistors are used on the same chip. Using differing gate thickness' requires additional fabrication processes and, hence, results in higher fabrication costs. Moreover, the larger gate oxide thickness can slow the device down unnecessarily. For low voltage CMOS signaling, the input/output pad must also be designed to prevent static leakage and prevent damage due to gate-source or gate-drain overvoltage.
FIG. 1
a
shows a block diagram of a conventional I/O pad
10
including an output buffer
12
and an input buffer
14
coupled to a common pad or pin
16
. The I/O pad
10
communicates signals to and from the pad
16
for the core logic
18
. As shown in
FIG. 1
c,
one known solution for preventing gate-source over voltage and reducing static leakage for an output buffer of an I/O pad is to use thick gate MOSFETS indicated as transistors
20
a
and
20
b.
As shown, pmos transistor
20
a
and nmos transistor
20
b
are configured as thick gate oxide devices having approximately a 70 angstrom gate oxide. The output buffer includes pre-buffers
22
a
and
22
b
which allow an output signal on the pad to be a logic “1” or a “0” depending upon which MOSFET is activated. As shown, the supply voltage to the buffer may be, for example, 3.3 volts or 1.5 volts. Hence, these configurations can accommodate different I/O pad supply voltages. However, a problem with the structure of
FIG. 1
b
is that the thick gate oxide transistor has to become too large to accommodate a 1.5 volt supply voltage to provide enough current and speed. Increasing the size of the thick gate devices will then increase the parasitic capacitance and slow down the operation of the device. It is desirable to reduce the gate oxide thickness and gate length to speed up the operation and reduce power consumption. As such,
FIG. 1
c
shows a conventional design that employs a thin gate nmos cascade arrangement using nmos transistors
24
a
and
24
b
in conjunction with a thick gate pmos transistor
20
a.
The structure of
FIG. 1
c
utilizes the cascading of the thin gate nmos devices such as thin gate oxide devices to prevent over voltage degradation to each of the respective thin gate devices. Voltages should be within normal operating voltages across junctions. However, this requires the use of a thick gate pmos device resulting in the use of several different gate oxide thickness technologies on the same I/O pad. The use of differing gate oxide technologies on the same chip can result in increased fabrication costs.
Consequently, a need exists for an I/O pad that can accommodate multiple source voltages using single gate oxide devices. It would be desirable to have an input/output pad containing I/O buffers that can handle different supply voltages while also reducing the cost of fabrication and improve operational speed.
REFERENCES:
patent: 5510731 (1996-04-01), Dingwall
patent: 5723987 (1998-03-01), Ronen
patent: 5821800 (1998-10-01), Le et al.
patent: 5966030 (1999-10-01), Schmitt et al.
patent: 6064227 (2000-05-01), Saito
patent: 6064229 (2000-05-01), Morris
Drapkin Oleg
Temkine Grigori
ATI International SRL
Le Don Phu
Tokar Michael
Vedder Price Kaufman & Kammholz
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