Three-level non-volatile semiconductor memory devices with...

Details Three-level non-volatile semiconductor memory devices with... Three-level non-volatile semiconductor memory devices with...

2006-12-07

2009-11-24

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S185180, C365S185120

Reexamination Certificate

active

07623383

ABSTRACT:
A non-volatile semiconductor memory device includes a page buffer comprising a lower latch block and an upper latch block, and a memory array that is connected to the lower latch block via a lower common bit line and that is connected to the upper latch block via an upper common bit line. The memory array includes a plurality of non-volatile memory cells, a lower even bit line and a lower odd bit line that are selectively connectable to the lower common bit line, an upper even bit line and an upper odd bit line that are selectively connectable to the upper common bit line, a first switch that electrically connects the lower even bit line to the upper even bit line in response to a first connection control signal and a second switch that electrically connects the lower odd bit line to the upper odd bit line in response to a second connection control signal.

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