Three dimensionally stacked non volatile memory units

Details Three dimensionally stacked non volatile memory units Three dimensionally stacked non volatile memory units

2009-04-16

2011-11-08

Mai, Son (Department: 2827)

Static information storage and retrieval

Systems using particular element

Resistive

C365S145000, C365S163000, C365S171000, C257S211000, C257S686000, C257SE21614, C257SE23085

Reexamination Certificate

active

08054673

ABSTRACT:
A memory unit including a first transistor spanning a first transistor region in a first layer of the memory unit; a second transistor spanning a second transistor region in a second layer of the memory unit; a first resistive sense memory (RSM) cell spanning a first memory region in a third layer of the memory unit; and a second RSM cell spanning a second memory region in the third layer of the memory unit, wherein the first transistor is electrically coupled to the first RSM cell, and the second transistor is electrically coupled to the second RSM cell, wherein the second layer is between the first and third layers, wherein the first and second transistor have an transistor overlap region, and wherein the first memory region and the second memory region do not extend beyond the first transistor region and the second transistor region.

REFERENCES:
patent: 6680499 (2004-01-01), Kumura et al.
patent: 6828689 (2004-12-01), Madurawe
patent: 6937505 (2005-08-01), Morikawa
patent: 7038261 (2006-05-01), Horii
patent: 7309885 (2007-12-01), Park et al.
patent: 7345899 (2008-03-01), Nirschl et al.
patent: 7453111 (2008-11-01), Ryoo et al.
patent: 7453716 (2008-11-01), Kim et al.
patent: 7479405 (2009-01-01), Park et al.
patent: 7642622 (2010-01-01), Yi et al.
patent: 2006/0028861 (2006-02-01), Han et al.
patent: 2006/0118913 (2006-06-01), Yi
patent: 2006/0120148 (2006-06-01), Kim
patent: 2007/0034908 (2007-02-01), Cho et al.
patent: 2007/0268742 (2007-11-01), Liu
patent: 2008/0038879 (2008-02-01), Kurjanowicz
patent: 2008/0106938 (2008-05-01), Ishii
patent: 2008/0203443 (2008-08-01), Wilson
patent: 2008/0203503 (2008-08-01), Asaq
patent: 2009/0039407 (2009-02-01), Vora
patent: 2009/0067212 (2009-03-01), Shimizu
patent: 2009/0185407 (2009-07-01), Park et al.
patent: 2009/0185410 (2009-07-01), Huai
Jung et al., Highly Cost Effective and High Performance 65nm S3(Stacked Single-Crystal Si) SRAM Technology . . . , 2005 Symposium on VLSI Technology Digest of Technical Papers, pp. 220-221.
PCT Search Report and Written Opinion dated Sep. 20, 2010.

Affiliated with

Also associated with

Rating

Three dimensionally stacked non volatile memory units does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Three dimensionally stacked non volatile memory units, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Three dimensionally stacked non volatile memory units will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4263858