Three-dimensional static random access memory device for avoidin

Details Three-dimensional static random access memory device for avoidin Three-dimensional static random access memory device for avoidin

1995-02-14

1995-09-19

Nelms, David C.

Static information storage and retrieval

Systems using particular element

Semiconductive

365154, 257382, 257385, 257903, G11C 1140, H01L 2910

Patent

active

054522471

ABSTRACT:
A gate electrode layer constituting a gate of a P-channel type MOS transistor formed on an upper layer is made of P-type polycrystal silicon and is connected to a diffusion region of an N-channel type MOS transistor formed on a lower layer by extending an end of the gate electrode layer into a contact hole above the diffusion region. Therefore, an aspect ratio of the contact hole becomes small and a coverage of a wiring for connecting the gate of the P-channel type MOS transistor and the diffusion region of the N-channel type MOS transistor is improved, so that the wiring is not snapped.

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"4 PMOS/2 NMOS Vertically Stacked CMOS-SRAM with 0.6 .mu.m Design Rule", Inoue et al, Symposium on VLSI Tech. Dig., pp. 39-40, (1989).
"Three-Dimensional SOI MOS Device Having a Possibility of Large Scale Integration", Sasaki et al, Electronic Material, pp. 74-79, Jun., 1985.

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