Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1991-02-15
1992-11-03
James, Andrew J.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257303, H01L 2978, H01L 2348, H01L 2946, H01L 2934
Patent
active
051609878
ABSTRACT:
Three-dimensional semiconductor structures are taught in which various device types are formed from a plurality of planar layers on a substrate. The major process steps include the formation of a plurality of alternating layers of material, including semiconductor and dielectric materials, forming a vertical access hole in the layers, processing the layers selectively to form active or passive semiconductor devices, and filling the access hole with a conductor. The ultimate structure includes a three-dimensional memory array in which entire dynamic memory cells are fabricated in a stacked vertical orientation above support circuitry formed on a planar surface.
REFERENCES:
patent: 4675980 (1987-06-01), Lade et al.
patent: 4700457 (1987-10-01), Matsukawa
patent: 4740826 (1988-04-01), Chatterjee
patent: 4809056 (1989-02-01), Shirato et al.
patent: 4845539 (1989-07-01), Inoue
`Process for Trench Planarization`, IBM Tech, vol. 29, No. 3, Aug. 86.
Faure Thomas B.
Meyerson Bernard S.
Nestork William J.
Pricer Wilber D.
Turnbull, Jr. John R.
International Business Machines - Corporation
James Andrew J.
Meier Stephen D.
Walter, Jr. Howard J.
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