Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
1998-07-27
2002-03-12
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S685000, C257S723000, C257S724000
Reexamination Certificate
active
06355976
ABSTRACT:
BACKGROUND OF INVENTION
1. Technical Field
The present invention relates generally to a three-dimensional package for massive layers of integrated circuit (IC) chips, on which logic circuits and/or memory arrays are disposed and interconnected in a novel way to permit addressing (i.e. selection) of the circuits and/or arrays on these circuit layers using a minimum number of connections and with the shortest propagation delays.
2. Brief Description of Prior Art
Today, most electronic packages are largely two-dimensional in arrangement. Typically, multiple chips are placed on a single planar module called a Multiple Chip Module (MCM). These modules are coarse in granularity, with feature sizes of 5 to 10 mils. Because of this coarse granularity, many metallization levels are required to wire the module. Typically, this category of IC packaging involves twenty to forty levels of metallization.
To reduce the number of metal layers, and thereby improve performance, newer 2-D modules use finer features such as thin-film wiring with line widths on the order of 10 to 20 &mgr;m. A typical arrangement is to place four chips on a single module to comprise a single microprocessor (MP). One chip is the computer (CPU), one chip is the storage control unit (SCU), while the remaining two chips are the cache memory. The average chip has dimensions of about 10 mm×10 mm. To allow for reasonable wiring, the module is likely to be 40 mm×40 mm. Even if placement algorithms are used to arrange chips and the function on the chips, typical chip-to-chip signal paths are of the order of the chip size, say 10 mm, For a transmission line of 15 &mgr;m width and lengths greater than 10 mm, line resistance becomes important and wiring rules are needed to restrict the signal length to achieve reasonable delays. Notably, the signal path length to main memory is much larger.
The MCMs described above are typically mounted on a card, and then the card is mounted on a board. Thus, the module is considered the first package level, the card the second level, and the board the third level. Clearly, there is much wasted space using such an arrangement that an opportunity is presented to explore newer more space-efficient packaging concepts for IC chips.
The fastest micro-processors using MCM packaging today have about 5 nanosecond (NS) cycle time. It is becoming increasingly evident that 2-D MCM packaging-techniques will not achieve significant improvements beyond 5 NS, making newer concepts extremely attractive.
Recognizing the limitations of two-dimensional MCM packaging technology, a number of companies including Irvine Sensors, Texas Instruments (TI) and Thomson have developed 3-D multilayer IC packaging techniques which involve stacking IC chips in the third dimension as shown in FIG.
2
. In general, the basic idea here is to control the size of the IC chips with precision dicing, stack them vertically, bond them together, polish one or more sides and deposit wires on the polished sides to interconnect the chips. While these prior art 3-D packaging approaches have been shown to work, they have many shortcomings and drawbacks, including: limitations on the number of IC chips which can be stacked vertically; very high manufacturing costs; and complex interconnection schemes.
Texas Instruments (TI) and Thompson are using a stacked tape-automated bonding (TAB) approach which has significant limitations in that the number of vertically-stacked chip layers is 20 or less.
Irvine Sensors Corporation (ISC) is pursing an approach that is more promising, although it too suffers from the following limitations: the number of layers of IC chips that can be stacked is limited to less than 100 because of alignment difficulties inherent in the manufacturing method; the number of layers which can be interconnected is limited unless each chip is individually personalized, a step that increases cost dramatically; the edge wiring density is low due to inaccurate alignment between the vertically disposed chips; the low yield and high cost because tested chips must have sizes with narrow tolerances to achieve certain alignment accuracy; the manufacturing process is too costly as the number of layers approaches 100; thermal and mechanical consideration add to manufacturing difficulties (i.e. heat must be carried to the edge of the stack for removal of IC chip layers and on an interchip bonding layer must be provided between to avoid delamination due to thermal mismatch); and the lack of flexibility in stack size.
In addition to the above-described activity in the 3-D packaging art, a number of 3-D IC packaging techniques have been proposed in the following U.S. Letters Patent. In U.S. Pat. No. 4,525,921, entitled “High-Density Electronic Processing Package-Structure and Fabrication”, a high density electronic package module has been proposed, comprising a stack of semiconductor chips having integrated circuitry on each chip. To permit the emplacement of thin film circuitry on the access ends, the access plane is etched to cut back the semiconductor material and then covered with passivation material. Thereafter, the passive material is lapped to uncover the ends of electrical leads on the chips. The leads are then connected to end plane wiring which is formed on two edges of stacked semiconductor chips. Chips are stacked in a supporting frame and bonded together using a thermally cured epoxy which remains over the whole surface area disposed between pairs of chips. In the arrangement disclosed in U.S. Pat. No. 4,525,921, the conductors which extend from the stacked chips extend beyond the ends of the chips by etching back the semiconductor material.
In U.S. Pat. No. 4,764,846 entitled “High Density Electronic Package Comprising Stacked Sub-Modules”, a high density electronic package has been proposed, wherein a stack of layer-like sub-modules have their edges secured to a stack-carrying substrate. The latter is in a plane perpendicular to the planes in which the sub-modules extend. Each sub-module has a cavity inside which one or more chips are located. Each cavity-providing sub-module may be formed either by securing a rectangular frame to a chip-carrying substrate or by etching a cavity in a single piece of material. In the latter case, chips are mounted on the flat surface of one sub-module, and located inside the cavity of the next sub-module. In this reference, an electronic module is formed by first constructing a plurality of individual chip carriers, each of which has a chip mounted in a cavity in the carrier. Then, the chip carriers are secured together in a laminated stack, and the stack as a unit, is secured to a wiring board or stack carrying substrate, wherein wiring which lies in a plane parallel to the plane of the chip. Thus, in the reference, chips are placed on substrates which are then placed in chip carriers and the chip carriers are stacked to form a module.
In U.S. Pat. No. 4,706,166 entitled “High-Density Electronic Modules-Process and Product”, a high density electronic module has also been proposed, wherein integrated circuit chips are stacked. The stacked chips are glued together with their leads along one edge so that all the leads of the stack are exposed on an access plane. Bonding bumps are formed at appropriate points on the access plane. A supporting substrate formed of light transparent material such as silicon, is provided with suitable circuitry and bonding bumps on its face. A layer of insulation is applied to either the access plane or the substrate face, preferably the latter. The bonding bumps on the insulation-carrying surface are formed after the insulation has been applied. The substrate face is placed on the access plane of the stack, their bonding bumps being aligned and then bonded together under heat and pressure. A layer of thermally conductive (but electrically non-conductive) adhesive material is inserted between the substrate and stack. The substrate and stack combination is then placed and wire bonded in a protective container having leads extending therethrough for extern
Clark Sheila V.
Perkowski Esq. P.C. Thomas J.
Reveo Inc
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