Three dimensional packaging configuration for multi-chip module

Details Three dimensional packaging configuration for multi-chip module Three dimensional packaging configuration for multi-chip module

1998-09-24

2000-10-17

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

257685, 257723, 257724, 257777, 257778, 257780, 438108, 438109, 361729, 361735, 361743, H01L 2302

Patent

active

061336262

ABSTRACT:
A multi-chip module (MCM) assembly has three stacked integrated circuit (IC) layers. The first IC layer is electrically flip-chip connected to a substrate. The back of the second IC layer may be glued to the back of the first IC layer, and the second and third IC layers are electrically flip-chip connected to each other. In one embodiment, the third IC layer is electrically connected to the substrate through a vertical interconnect element for high circuit density. In another, the second IC layer is electrically connected to the substrate using wire bonding for greater post-fabrication customization flexibility. In still another embodiment, the MCM assembly comprises two stacked IC layers where the second IC layer is electrically flip-chip connected to the first IC layer and the second layer is electrically connected to the substrate through a vertical interconnect element. By directly connecting IC layers, higher circuit density, lower trace impedance, and lower cross-talk or electrical noise susceptibility is achieved over that presently offered by most current MCM assemblies. The assembly accommodates different sized IC layers, multiple ICs on each layer, and different technology-based IC layers and ICs within each layer, providing the user with high design flexibility within a single multi-chip assembly.

REFERENCES:
patent: 4706166 (1987-11-01), Go
patent: 5128831 (1992-07-01), Fox, III et al.
patent: 5138438 (1992-08-01), Masayuki et al.
patent: 5222014 (1993-06-01), Lin
patent: 5229647 (1993-07-01), Gnadinger
patent: 5331235 (1994-07-01), Chun
patent: 5422435 (1995-06-01), Takiar et al.
patent: 5760478 (1999-08-01), Bozso et al.
patent: 5790384 (1998-08-01), Ahmad
"Method of Constructing a Central Processing Unit Using Light Communications", IBM Technical Disclosure Bulletin, vol. 33, No. 11, Jan. 4, 1991.

Affiliated with

Also associated with

Rating

Three dimensional packaging configuration for multi-chip module does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Three dimensional packaging configuration for multi-chip module , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Three dimensional packaging configuration for multi-chip module will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-471967