Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2006-12-26
2010-06-22
Pham, Thanh V (Department: 2894)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S113000, C438S458000, C438S618000, C257SE21597, C257SE23068
Reexamination Certificate
active
07741152
ABSTRACT:
A method of making a three-dimensional package, including: (a) providing a wafer; (b) forming at least one blind hole; (c) forming an isolation layer; (d) forming a conductive layer; (e) forming a dry film; (f) filling the blind hole with a solder; (g) removing the dry film; (h) patterning the conductive layer; (i) removing a part of the lower surface of the wafer and the isolation layer, so as to expose the conductive layer; (j) stacking a plurality of the wafers, and performing a reflow process; and (k) cutting the stacked wafers, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer is inserted into the solder of the lower wafer, so as to enhance the joint between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.
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Cheng Po-Jen
Huang Min-Lung
Lin Chian-Chi
Lo Jian-Wen
Su Ching-Huei
Advanced Semiconductor Engineering Inc.
Nguyen Duy T
Pham Thanh V
Volentine & Whitt P.L.L.C.
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