Three-dimensional, one-transistor cell arrangement for dynamic s

Details Three-dimensional, one-transistor cell arrangement for dynamic s Three-dimensional, one-transistor cell arrangement for dynamic s

1988-10-18

1990-07-17

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Capacitors

357 236, G11C 1124, H01C 2978

Patent

active

049425544

ABSTRACT:
In a three-dimensional, one-transistor cell arrangement for dynamic semiconductor memories, whereby the capacitor for the charges to be stored is fashioned as a trench capacitor in the substrate and, separated by an insulating layer, is arranged under the selection transistor comprising an insulated gate electrode and is connected to the source/drain zone thereof in electrically conductive fashion, and whereby the source/drain zones of the selection transistor are contained in a recrystallized silicon layer applied above the insulating layer, the electricity conductive contact to the capacitor is formed by an asymmetrical trench expansion introduced into the substrate in the upper part of the trench, this asymmetrical trench expansion being filled with polycrystalline silicon having the same doping as in the trench, and the source/drain zones are produced such by ion implantation in the recrystallized silicon layer that the source zone overlaps the electrically conductive contact in the asymmetrical trench expansion. The memory cell arrangement provided enables an extremely compact memory cell having an area of less than 3 .mu.m.sup.2, enabling this on the basis of simple process steps; the arrangement and method can be employed in the manufacture of 64 megabit Drams.

REFERENCES:
patent: 4728623 (1988-03-01), Lu et al.
patent: 4801989 (1989-01-01), Taguchi
patent: 4830978 (1984-05-01), Teng et al.
Japanese Abstract, vol. 9, No. 298, 60-136366, Jul. 19, 1985 by Shimizu.
M. Ohkura, "A Three-Dimensional Dram Cell of Stacked Switching-Transistor in Soi (SSS)", IEEE, Digest of Technical Papers, 1985, pp. 718-721.

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