Three dimensional NAND memory

Details Three dimensional NAND memory Three dimensional NAND memory

2007-03-27

2010-12-14

Lee, Eugene (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S067000, C257SE29131, C257SE29134, C257SE29262

Reexamination Certificate

active

07851851

ABSTRACT:
A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell. A semiconductor active region of the first memory cell is formed epitaxially on a semiconductor active region of the second memory cell, such that a defined boundary exists between the semiconductor active region of the first memory cell and the semiconductor active region of the second memory cell.

REFERENCES:
patent: 4786615 (1988-11-01), Liaw et al.
patent: 5874760 (1999-02-01), Burns, Jr. et al.
patent: 5915167 (1999-06-01), Leedy et al.
patent: 5929477 (1999-07-01), McAllister, Jr. et al.
patent: 5981350 (1999-11-01), Geusic et al.
patent: 6034882 (2000-03-01), Johnson et al.
patent: 6180458 (2001-01-01), Krautschneider et al.
patent: 6211015 (2001-04-01), Noble
patent: 6242775 (2001-06-01), Noble
patent: 6388293 (2002-05-01), Ogura et al.
patent: 6580124 (2003-06-01), Cleeves et al.
patent: 6727544 (2004-04-01), Endoh et al.
patent: 6744094 (2004-06-01), Forbes
patent: 6858899 (2005-02-01), Mahajani et al.
patent: 6881628 (2005-04-01), Rudeck
patent: 6881994 (2005-04-01), Lee et al.
patent: 6906953 (2005-06-01), Forbes
patent: 7009888 (2006-03-01), Masuoka et al.
patent: 7115476 (2006-10-01), Izumida
patent: 7253055 (2007-08-01), Mokhlesi et al.
patent: 7378702 (2008-05-01), Lee
patent: 7514321 (2009-04-01), Mokhlesi et al.
patent: 2002/0028541 (2002-03-01), Lee et al.
patent: 2002/0058381 (2002-05-01), Lee
patent: 2003/0048666 (2003-03-01), Eldridge et al.
patent: 2005/0035399 (2005-02-01), Masuoka et al.
patent: 2005/0133851 (2005-06-01), Forbes
patent: 2005/0167759 (2005-08-01), Matsui et al.
patent: 2005/0184329 (2005-08-01), Prall
patent: 2005/0224847 (2005-10-01), Masuoka et al.
patent: 2006/0001078 (2006-01-01), Liu
patent: 2008/0237602 (2008-10-01), Mokhlesi et al.
patent: 1179850 (2002-02-01), None
patent: 7-235649 (1995-09-01), None
patent: WO 02/15277 (2002-02-01), None
NG, Complete Guide to Semiconducter Devices, 2002, John Wiley & Sons, 2nd Ed., pp. 353-358.
Office Action dated Nov. 10, 2008 received in U.S. Appl. No. 11/691,917.
Office Action dated Feb. 5, 2009 received in U.S. Appl. No. 11/691,858.
Office Action dated Jul. 1, 2009 received in U.S. Appl. No. 11/691,901.
Office Action dated Jul. 7, 2009 received in U.S. Appl. No. 11/691,885.
Office Action dated Jan. 12, 2010 received in U.S. Appl. No. 11/691,885.
Office Action dated Jan. 20, 2010 received in U.S. Appl. No. 11/691,858.
Pein, Howard B. et al., “Performance of the 3-D Sidewall Flash EPROM Cell”, IEDM Conf. Proc., (1993), pp. 2.1.1-2.1.4.
Endoh, Tetsuo et al., “Novel Ultra High Density Flash Memory with a Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Conf. Proc., (2001), pp. 2.3.1-2.3.4.
Endoh, Tetsuo et al., “Novel Ultrahigh-Density Flash Memory With a Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEEE Transactions on Electron Devices, (2003), pp. 945-951, vol. 50, No. 4.
Sato, Nobuhiko et al., “Hydrogen annealed silicon-on-insulator”, Appl. Phys. Lett , (1994), pp. 1924-1926, vol. 65, No. 15.
Zhong, Lei et al., “Surface modification of silicon (111) by annealing at high temperature in hydrogen”, Appl. Phys. Lett , (1996), pp. 2349-2351, vol. 68, No. 17.
Zaman, Rownak J. et al., “Effects of Hydrogen Annealing Process Conditions on Nano Scale Silicon (011) Fins”, Mater. Res. Soc. Symp. Proc., (2005), pp. J3.1.1-J3.1.5, vol. 872.
Lee, Jeong-Soo et al., “Hydrogen Annealing Effect on DC and Low-Frequency Noise Characteristics in CMOS FinFETs”, IEEE Electron Device Letters, (2003), pp. 186-188, vol. 24, No. 3.
U.S. Appl. No. 11/691,858, filed Mar. 27, 2007, Nima Mokhlesi et al.
U.S. Appl. No. 11/691,885, filed Mar. 27, 2007, Nima Mokhlesi et al.
U.S. Appl. No. 11/691,901, filed Mar. 27, 2007, Nima Mokhlesi et al.
U.S. Appl. No. 11/691,917, filed Mar. 27, 2007, Nima Mokhlesi et al.

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