Static information storage and retrieval – Format or disposition of elements
Reexamination Certificate
2002-06-27
2004-03-23
Lam, David (Department: 2818)
Static information storage and retrieval
Format or disposition of elements
C365S052000, C365S063000
Reexamination Certificate
active
06711043
ABSTRACT:
BACKGROUND
A three-dimensional solid-state memory array is a relatively slow memory, but it is a far more economical means of storing data than other semiconductor memory types. The relatively slow read access time of three-dimensional memory arrays is not a drawback when the data read from the memory array is digital audio or digital images. However, when the data read from the memory array is code executed by a host device, a user can notice the delay because the clock speed of the host device is faster than what can typically be supported by a three-dimensional memory array. There is a need, therefore, for adapting three-dimensional memory arrays for use in faster environments.
Additionally, several caching topologies are known for use with two-dimensional memory arrays. In one caching topology, separate cache memory and two-dimensional primary memory chips are used. One disadvantage to this multi-chip arrangement is that chip-to-chip busses add cost and power to the system. In another caching topology, the cache memory and the two-dimensional primary memory are integrated in a single silicon chip in the same two-dimensional plane. Although this arrangement eliminates the inter-chip data transmission delay encountered with the multi-chip arrangement, area on the silicon chip is need for busses between the cache memory and the primary memory, thereby increasing die size and cost. Accordingly, there is also a need for a new caching topology that will overcome these disadvantages.
SUMMARY
The present invention is defined by the following claims, and nothing in this section should be taken as a limitation on those claims.
By way of introduction, the preferred embodiments described below provide a three-dimensional memory cache system. In one preferred embodiment, a modular memory device removably connectable to a host device is provided. The modular memory device comprises a substrate, a cache memory array, a three-dimensional primary memory array, and a modular housing. The cache memory array and the three-dimensional primary memory array can be on the same or separate substrates in the modular housing. In another preferred embodiment, an integrated circuit is provided comprising a substrate, a cache memory array in the substrate, and a three-dimensional primary memory array above the substrate. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
The preferred embodiments will now be described with reference to the attached drawings.
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Friedman David R.
Moore Christopher S.
Scheuerlein Roy E.
Schneider James E.
Steere Daniel C.
Brinks Hofer Gilson & Lione
Lam David
Matrix Semiconductor Inc.
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