Three-dimensional memory array and method of fabrication

Details Three-dimensional memory array and method of fabrication Three-dimensional memory array and method of fabrication

2006-08-15

2006-08-15

Whitehead, Jr., Carl (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

C257S530000, C257SE27103

Reexamination Certificate

active

07091529

ABSTRACT:
A multi-level memory array is described employing rail-stacks. The rail-stacks include a conductor and semiconductor layers. The rail-stacks are generally separated by an insulating layer used to form antifuses. In one embodiment, one-half the diode is located in one rail-stack and the other half in the other rail-stack.

REFERENCES:
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patent: 4569121 (1986-02-01), Lim et al.
patent: 5451811 (1995-09-01), Whitten et al.
patent: 6034882 (2000-03-01), Johnson et al.
patent: 6051851 (2000-04-01), Ohmi et al.
patent: 6300664 (2001-10-01), Kuroi et al.

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