Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
1998-08-20
2001-07-03
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S786000, C257S778000, C257S723000
Reexamination Certificate
active
06255736
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a three-dimensional multichip module (MCM) and a semiconductor chip which can be used in this MCM. More particularly, the present invention relates to a technique for designing and manufacturing a semiconductor chip, such as a standard cell and an embedded array which can be used in an MCM, using computer-aided design (CAD). Further, the present invention relates to a storage medium for storing data used when design using CAD is carried out.
2. Description of the Related Art
Gate array, standard cell and embedded array are conventionally known methods for efficiently designing a semicustom LSI, as means for designing an Application Specific Integrated circuit (ASIC), which simply realizes a device for specific application using CAD.
A gate array is formed by preparing a master wafer beforehand, having transistors laid thereon in an array, and adding interconnections to the master wafer so as to produce a logic system. As shown in the example of
FIG. 1
, bonding pads (I/O pads)
101
are provided at the peripheral region of a chip, and a random logic block
102
is provided in the remaining region (central region) of the chip. In the random logic block
102
, transistors are laid in an array.
However, a gate array architecture cannot be used to realize a large-scale macrocell such as a CPU or a memory. For this reason, a standard cell design methodology was introduced to simply realize a large-scale macrocell. To produce a standard cell, optimally designed and verified macrocells, registered beforehand in a CAD design database, are assembled in a predetermined layout using CAD. As shown in the example of
FIG. 2
, bonding pads
201
are provided at the peripheral region of the chip, and macrocells, comprising a CPU core
202
, a RAM
203
, a RAMBUS interface
204
, a PLL
205
and a ROM
206
, are provided in central region of the chip. These macrocells are directly connected to each other by interconnections.
The standard cell architecture enables large-scale macrocells to be formed easily, but has a disadvantage that the fabrication of each macrocell must start from the transistor unit level, or from the beginning of the fabrication process, lengthening development time.
Therefore, an embedded array architecture, in which standard cell macrocells are buried in the random logic block of a gate array, has been proposed.
This embedded array is manufactured after the number of gates and the types of macrocells to be contained within the random logic block have been decided. In other words, the embedded array is customised after the wafer process has been commenced but prior to the metallization process. In this state, completion of the logic design is awaited and, after a logic simulation has been carried out, the embedded array is completed by providing interconnections to the random logic block. As shown in the example of
FIG. 3
, bonding pads
301
are provided at the peripheral region of the chip, and macrocells comprising a CPU core
302
, a RAM
303
, a RAMBUS interface
304
, a PLL
305
and a ROM
306
, are provided in central region of the chip. In addition, a random logic block
307
is provided in order to realize the functions of these macrocells.
This embedded array comprises the random logic block, and therefore the customization of the embedded array do not need to be started from the transistor unit level. Consequently, time needed to develop the standard cell can be reduced. Moreover, changes to the circuits of the random logic block can dealt with simply by changing the interconnections.
However, on the conventional embedded array or the standard cell, no bump pads are prepared as the components of the cells for connecting to another chip directly above or below the embedded array or the standard cell. Then, when assembling an MCM with a chip fabricated by the conventional embedded array or the standard cell approach in combination with another pre-existing chip, these chips must be disposed in a side-by-side configuration, or two-dimensional configuration as shown in FIG.
4
A and FIG.
4
B.
FIG. 4A
is a top view, and
FIG. 4B
, a side view. As shown in FIG.
4
A and
FIG. 4B
, a chip
401
and a chip
402
are provided on a lead frame
400
. Chip
401
is the conventional embedded array or the standard cell, and chip
402
is the pre-existing chip. Since it is not possible to stack the chips
401
and
402
three-dimensionally one above the other, they are arranged side by side on the lead frame
400
. Then the right side bonding pads
403
on chip
401
, and the left side bonding pads
404
on chip
402
are connected by bonding wires
407
. And the left side bonding pads
403
on chip
401
and leads
406
are connected by bonding wires
405
. Further, the right side bonding pads
404
on the chip
402
and leads
409
are connected by bonding wires
408
.
The above structure, wherein multiple chips are two-dimensionally provided side by side, makes it impossible to reduce the area of the frame to less than the total area of the chips. As a result, the mounting area of the package cannot be made small.
Furthermore, the conventional MCM has a problem that electrical signals exchanged between the chips are delayed due to the long distance of the interconnections between the chips. As a consequence, it has been difficult to achieve high-speed executions with the conventional MCM. Furthermore, in a two-dimensional chip structure, it has been difficult to reduce noise generated by electrical signals exchanged between the chips.
SUMMARY OF THE INVENTION
The present invention has been achieved in order to solve the conventional problems described above and aims to provide a MCM of smaller scale.
It is another object of the present invention to provide a three-dimensional MCM using an ASIC, such as a standard cell or an embedded array, as a base chip.
It is yet another object of the present invention to provide a three-dimensional MCM wherein distance of interconnections between chips is short, delay of electrical signals exchanged between the chips is reduced, and high-speed behaviour is achieved.
It is yet another object of the present invention to provide a three-dimensional MCM in which noise generation of electrical signals exchanged between the chips is reduced.
It is yet another object of the present invention to provide an ASIC, such as a high general versatility standard cell or embedded array, which can be easily assembled in a three-dimensional MCM.
It is yet another object of the present invention to provide a manufacturing method whereby a small-scale high-speed high-performance three-dimensional MCM, which uses a standard cell as the base chip, can be easily designed and manufactured.
It is yet another object of the present invention to provide a manufacturing method whereby a small-scale high-speed high-performance three-dimensional MCM, which uses an embedded array as the base chip, can be easily designed and manufactured.
It is yet another object of the present invention to provide a storage medium for storing data needed for designing layout and the like of a macrocell, a bump pad and interconnections, and to easily and quickly manufacture a three-dimensional MCM which uses a standard cell as a base chip.
It is yet another object of the present invention to provide a storage medium for storing data needed for designing layout and the like of a macrocells, a random logic block and a bump pad, and to easily and quickly manufacture a three-dimensional MCM which uses an embedded array as a base chip.
In order to achieve the above objects, a multichip module (MCM) comprising a three-dimensional structure, wherein a base chip and an external chip are connected by a bump, constitutes a first aspect. In other words, the first aspect of the present invention is an MCM comprising: a base chip having: a bonding pad provided at a peripheral region thereof; an internal circuit containing macrocells provided in and at proximity to a central region of the base chip; and a b
Clark Sheila V.
Foley & Lardner
Kabushiki Kaisha Toshiba
LandOfFree
Three-dimensional MCM, method for manufacturing the same,... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Three-dimensional MCM, method for manufacturing the same,..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Three-dimensional MCM, method for manufacturing the same,... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2434883