Three-dimensional integrated CMOS-MEMS device and process...

Semiconductor device manufacturing: process – Making device or circuit responsive to nonelectrical signal – Physical stress responsive

Reexamination Certificate

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Details

C438S109000, C438S050000, C438S051000, C438S014000, C438S461000, C257S254000, C216S052000

Reexamination Certificate

active

06835589

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the manufacture of very large-scale integrated devices including CMOS logic devices and micro-electromechanical (MEMS) devices for the next generation of data storage. In particular, the invention relates to fabrication of three-dimensional device structures including CMOS and MEMS chips.
BACKGROUND OF THE INVENTION
The use of micro-electromechanical systems (MEMS) and nano-electromechanical systems (NEMS) for ultrahigh density data storage has recently been reported. This approach to data storage utilizes a thermomechanical local probe technique with large arrays of nanometer-scale tips, such as are now used in atomic-force microscope and scanning-tunneling microscope technology. In this technique, a read/write operation is performed by heating a cantilever mechanism, causing a tip to contact a thin film storage medium and either create or detect depressions made therein.
Some details of the design of MEMS structures for data storage have been recently published in IBM J. Res. Develop. 44, 323 (2000) and in Sensors and Actuators 80, 100 (2000).
An individual cantilever cell is shown schematically in
FIG. 1A
(cross-section view) and
FIG. 1B
(plan view). The MEMS chip
1
, typically of silicon, is processed to yield a silicon cantilever
10
with a tip
11
and a heater
13
. As shown in
FIG. 1A
, the cantilever structure
10
is formed on a layer at the surface of chip
1
, and a cavity is then etched in the bulk silicon behind cantilever
10
. Applying electrical power via the through connection
15
causes a temperature increase in the heater and tip, which is in contact with storage medium
12
(typically a thin polymer film on a silicon substrate). The combination of tip pressure on the storage medium and the tip heating causes the tip to create an indentation in the storage medium, thereby realizing thermomechanical data writing with very high bit a real densities.
A conventional 2-dimensional arrangement for controlling the MEMS chip
1
is shown schematically in FIG.
2
. The MEMS chip
1
, which includes a large number of individual cells, is electrically controlled by multiplex drivers
2
having conventional wirebonding connections to the edge of chip
1
. There are limitations inherent in the 2-dimensional arrangement of electrical connections. For example, as the number of cells in chip
1
increases, it becomes more difficult to provide electrical isolation between cells; at the same time, higher power is required to address the cell array while the size of individual connections decreases.
Accordingly, there is a need for a 3-dimensional integration scheme in which MEMS devices and their control devices (such as CMOS logic chips) may be interconnected, in order to overcome the electrical limitations of the conventional 2-dimensional configuration.
SUMMARY OF THE INVENTION
The present invention addresses the above-described need by providing a method for integrating a chip having a micromechanical device and a chip having an electronic device. In particular, the invention provides a method for vertical integration of a chip and a MEMS where the MEMS may make contact with a surface (such as the surface of a film serving as a storage device) and have mechanical motion with respect to that surface in the vertical direction.
According to one aspect of the invention, a method is provided for fabricating an integrated structure including a micro-electromechanical system (MEMS) and a chip for delivering signals to the MEMS. The MEMS is formed on a substrate, and has an anchor portion by which it is connected to the substrate (In one embodiment of the invention, the MEMS is a cantilever which overhangs a cavity in the substrate, and is anchored to the substrate at the anchor portion.) A conductor is formed which extends from the anchor portion of the MEMS through the MEMS substrate. The chip is attached to the MEMS substrate in a direction normal to the substrate surface, so as to make a conductive path from the chip to the MEMS. The chip may be attached by (1) forming a C4 metal pad on the chip, aligning the C4 metal pad to the conductor, and then bonding the C4 metal to the conductor; or (2) forming a metal stud on the chip, aligning the stud to the conductor; and bonding the stud to the conductor. It is preferable that the MEMS substrate be thinned before the chip is attached; this may conveniently be done by first attaching a carrier plate, and then removing the carrier plate after the attaching process is complete.
According to another aspect of the invention, a method is provided for fabricating an integrated structure including a micro-electromechanical system (MEMS) and a chip for delivering signals to the MEMS. In this method, the MEMS is formed on the substrate and has an anchor portion with an opening therein, and a conductor is formed in the opening of the anchor portion. The MEMS substrate is then removed, thereby exposing an underside of the MEMS and the conductor. The chip is then attached to the anchor portion of the MEMS in a direction normal to the substrate surface, so as to make a conductive path from the chip to the MEMS. Before the substrate is removed, it is convenient to deposit a layer overlying the MEMS, and to attach a carrier plate thereto; the carrier plate is removed after the MEMS and the chip are attached. The connection between the chip and the MEMS is through a metal stud formed on the chip, in an opening in a layer overlying the chip. The underside of the MEMS is thus spaced from the chip by a distance corresponding to the thickness of that layer.
According to an additional aspect of the invention, a vertically integrated structure is provided in which a micro-electromechanical system (MEMS) and a chip for delivering signals to the MEMS are connected. The structure includes a layer overlying a portion of the chip and having an opening therein; a metal stud in the opening and contacting the chip; and the MEMS having an anchor portion and an end portion extending horizontally therefrom. The anchor portion is attached to the layer and includes a conductor in contact with the metal stud. The MEMS is spaced from the chip by a distance corresponding to a thickness of the layer; the MEMS may then contact another layer spaced from the chip in a vertical direction.


REFERENCES:
patent: 5475318 (1995-12-01), Marcus et al.
patent: 6250933 (2001-06-01), Khoury et al.
patent: 6291140 (2001-09-01), Andreoli et al.
patent: 6473361 (2002-10-01), Chen et al.
patent: 6475822 (2002-11-01), Eldridge et al.
patent: 6583411 (2003-06-01), Altmann et al.
patent: 6586133 (2003-07-01), Teeters et al.
patent: 6645145 (2003-11-01), Dreschel et al.
patent: 6651325 (2003-11-01), Lee et al.
patent: 2002/0096967 (2002-07-01), Ma et al.
patent: 2003/0038703 (2003-02-01), Weaver et al.
patent: 2003/0076649 (2003-04-01), Speakman
patent: 2003/0081651 (2003-05-01), Gianchandani et al.
patent: 2003/0119221 (2003-06-01), Cunningham et al.
patent: 2003/0137389 (2003-07-01), Weaver et al.
“3-D Integration using wafer bonding,” J-Q Lu et al.—Article—pp. 1-7.
“Ultrathin GaAs space solar cell devices,” Hardingham et al.,1996 IEEE, 25th PVSC; May 13-17, 1996, Washington, DC.
“Residual thermomechanical stresses in thinned-chip assemblies,” Leseduarte et al., IEEE Transactions on components and packaging technologies, vol. 23, No. 4, Dec. 2000.
“High bandwith interconnects via a novel chip-stack package,” Eric Beyne, IMEC, Leuven, Belgium, Solid State Technology, Apr. 2002 pp. S19-S22.
“The “Millipede”—more than one thousand tips for future AFM data storage,” Vettiger et al., IBM Journal of Research and Development, vol. 44, No. 3, May 2000, pp. 323-338.
“VLSI-NEMS chip for parallel AFM data storage,” Despont et al., Reprinted from Sensors and Actuators 80 (2000) 100-107.
“Automated handling of ultra-thin silicon wafers” F. A. Tony Schraub, Solid State Technology, Sep. 2002, pps. 59-64.
“Saving energy and natural resource by micro-nanomachining” Masayoshi Esashi, Technical Digest: 15th IEEE Conference on Micro-Electro Mechanica

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