Three-dimensional hierarchical coupling extraction

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C716S030000

Reexamination Certificate

active

07669152

ABSTRACT:
Apparatus, systems, and methods are provided for processing integrated circuit chip design. A three-dimensional Monte Carlo random-walk process may be applied to a cell in a hierarchical description of the layout of the chip to extract information regarding the cell. The information may include coupling resistance, capacitance, inductance, or combinations thereof. A neighborhood of the cell may be built and data correlated to the neighborhood may be stored. Such a technique may be applied from a bottom level to a top level of the hierarchical description of the chip layout.

REFERENCES:
patent: 5452224 (1995-09-01), Smith, Jr. et al.
patent: 5706206 (1998-01-01), Hammer et al.
patent: 5761080 (1998-06-01), DeCamp et al.
patent: 5901063 (1999-05-01), Chang et al.
patent: 6128768 (2000-10-01), Ho
patent: 6175947 (2001-01-01), Ponnapalli et al.
patent: 6643831 (2003-11-01), Chang et al.
patent: 6892366 (2005-05-01), Teig et al.
patent: 7155689 (2006-12-01), Pierrat et al.
patent: 2004/0128642 (2004-07-01), Beaudette
patent: 2005/0108669 (2005-05-01), Shibuya
patent: 2006/0053394 (2006-03-01), Batterywala et al.
patent: 2006/0206841 (2006-09-01), Batterywala
patent: 2007/0271543 (2007-11-01), Alpert et al.
Aurenhammer, F. , “Voronoi diagrams: A survey of a fundamental geometric data structure”,ACM Comput. Survey, 23, (1991),345-405.
Batterywala, S. H., et al., “Variance reduction in Monte Carlo capacitance extraction”,18th International Conference on VLSI Design, 2005., (2005),85-90.
Brambilla, A. , et al., “A statistical algorithm for 3D capacitance extraction”,IEEE Microwave and Guided Wave Letters, [see also IEEE Microwave and Wireless Components Letters], 10(8), (2000),304-306.
Brambilla, A. , et al., “Measurements and extractions of parasitic capacitances in ULSI layouts”,IEEE Transactions on Electron Devices, 50(11), (2003),2236-2247.
Brambilla, A. , et al., “Statistical method for the analysis of interconnects delay in submicrometer layouts”,IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 20(8), (2001),957-966.
Garg, A. , et al., “Accurate high-speed performance prediction for full differential current-mode logic: the effect of dielectric anisotropy”,IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(2), (1999),212-219.
Iverson, Ralph B., et al., “A floating random-walk algorithm for extracting electrical capacitance”,Mathematics and Computers in Simulation, 55(1-3), (2001),59-66.
Jere, J. N., et al., “An improved floating-random-walk algorithm for solving the multi-dielectric Dirichlet problem”,IEEE Transactions on Microwave Theory and Techniques, 41(2), (1993),325-329.
Le Coz, Y. L., et al., “A stochastic algorithm for high speed capacitance extraction in integrated circuits”,Solid-State Electronics, 35(7), (1992),1005-1012.
Le Coz, Y. L., et al., “Performance of random-walk capacitance extractors for IC interconnects: a numerical study”,Solid-State Electronics, 42(4), (1998),581-588.
Maffezzoni, P. , et al., “A statistical approach to derive an electrical port model of capacitively coupled interconnects”,IEEE Transactions on Circuits and Systems I: Regular Papers, [see also Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on], 51(4), (2004),797-807.
Maffezzoni, P. , et al., “Analysis of substrate coupling by means of a stochastic method”,IEEE Electron Device Letters, 23(6), (2002),351-353.
Maffezzoni, P. , et al., “Study of statistical approaches to the solution of linear discrete and integral problems”,IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, [see also Circuits and Systems I: Regular Papers, IEEE Transactions on], 50(9), (2003), 1153-1161.
Papadopoulou, E., “Critical area computation for missing material defects in ULSI circuits”,IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 20(5), (2001),583-597.
Papadopoulou, E. , et al., “The L∞ Voronoi Diagram of Segments and VLSI Applications”,International Journal of Computational Geometry&Applications, 11(5), (2001),503-528.
Prabhakaran, M. M., “Deterministic and Randomized Methods for Capacitance Estimation”,BTech Project Report, Indian Institute of Technology, Bombay, (2000), 1-34.
Royer, G. M., “Monte Carlo Procedure for Theory Problems Potential”,IEEE Transactions on Microwave Theory and Techniques, 19(10), 1971),813-818.
Sadiku, Matthew N., “Monte Carlo solution of axisymmetric potential problems”,IEEE Transactions on Industry Applications, 29(6), (1993),1042-1046.
Sadiku, M. , et al., “Solution of Dirichlet problems by the Exodus method”,IEEE Transactions on Microwave Theory and Techniques, 40(1), (1992),89-95.
Schlott, R., “A Monte Carlo method for the Dirichlet problem of dielectric wedges”,IEEE Transactions on Microwave Theory and Techniques, 36(4), (1998),724-730.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Three-dimensional hierarchical coupling extraction does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Three-dimensional hierarchical coupling extraction, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Three-dimensional hierarchical coupling extraction will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4193314

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.