Three-dimensional graphics accelerator which implements multiple

Details Three-dimensional graphics accelerator which implements multiple Three-dimensional graphics accelerator which implements multiple

1996-07-01

1999-02-23

Tung, Kee M.

Computer graphics processing and selective visual display system

Computer graphic processing system

Plural graphics processors

345522, 345526, 345506, G06F 1580

Patent

active

058749691

ABSTRACT:
A 3-D graphics accelerator which includes a command block or preprocessor, a plurality of floating point processors or blocks, and one or more draw processors or blocks. The 3-D graphics accelerator includes a plurality of direct data channels or point-to-point buses, collectively referred to as the CF bus, which connect the command preprocessor to each of the plurality of floating point processors. The 3-D graphics accelerator also includes a plurality of direct data channels or point-to-point buses, collectively referred to as the FD bus, which connect the plurality of floating point processors to each of the draw processors. The system of the present invention also implements a bus from the command preprocessor directly to the draw processors, referred to as the CD bus, which uses portions of the above direct data channels. The CD bus shares or "borrows" the data lines from the CF bus a id the FD bus and uses the floating point processors as buffer chips. This allows implementation of a "logical" bus while using existing bus lines.

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Deering, et al., "FBRAM: A New Form of Memory Optimized for 3D Graphics," Computer Graphics Proceedings, Annual Conference Series, 1994, pp. 167-174.
Deering, Michael, "Geometry Compression," Computer Graphics Proceedings, Annual Conference Series, 1995, pp. 13-20.
Deering, et al., "Leo: A System for Cost Effective 3D Shaded Graphics," Computer Graphics Proceedings, Annual Conference Series, 1993, pp. 101-108 .

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