Three-dimensional complementary field effect transistor process

Details Three-dimensional complementary field effect transistor process Three-dimensional complementary field effect transistor process

1995-11-08

1999-07-20

Loke, Steven H.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257329, 257334, 257369, 257401, H01L 2976, H01L 2994, H01L 31062, H01L 31113

Patent

active

059259094

ABSTRACT:
A field effect transistor has a short gate and is fabricated by: doping the bottom surface of a depression to form a relatively lightly doped region in the bottom of the depression; forming the gate of the field effect transistor on the sidewall of the depression such that the gate is insulated from the sidewall by a thin insulating layer; and implanting dopants to form the drain region and the source region of the transistor using the gate to mask a part of the relatively lightly doped region. The part of the relatively lightly doped region which is masked by the gate during implanting of the source and drain regions constitutes a lightly doped drain region of the transistor. The drain of the transistor is formed into the bottom of the depression. The length of the gate is primarily determined by the depth and/or profile of the sidewall. The source-to-drain on-resistance of the transistor is low because the transistor does not have a lightly doped source region. The transistor has high quality gate oxide because the sidewall of the depression upon which the gate oxide is grown is substantially free of ion impact damage.

REFERENCES:
patent: 3500142 (1970-03-01), Kahng
patent: 4203158 (1980-05-01), Frohman-Bentchkowsky et al.
patent: 4267632 (1981-05-01), Shappir
patent: 4597827 (1986-07-01), Nishitani et al.
patent: 4698787 (1987-10-01), Mukherjee et al.
patent: 4698900 (1987-10-01), Esquivel
patent: 4763177 (1988-08-01), Paterson
patent: 4780424 (1988-10-01), Holler et al.
patent: 4814286 (1989-03-01), Tam
patent: 4849363 (1989-07-01), Coffey et al.
patent: 4890144 (1989-12-01), Teng et al.
patent: 4929988 (1990-05-01), Yoshikawa
patent: 4964080 (1990-10-01), Tzeng
patent: 5017977 (1991-05-01), Richardson
patent: 5047812 (1991-09-01), Pfiester
patent: 5049515 (1991-09-01), Tzeng
patent: 5053842 (1991-10-01), Kojima
patent: 5073513 (1991-12-01), Lee
patent: 5077230 (1991-12-01), Woo et al.
patent: 5077691 (1991-12-01), Haddad et al.
patent: 5087584 (1992-02-01), Wada et al.
patent: 5102814 (1992-04-01), Woo
patent: 5103274 (1992-04-01), Tang et al.
patent: 5108937 (1992-04-01), Tsai et al.
patent: 5111270 (1992-05-01), Tzeng
patent: 5120671 (1992-06-01), Tang et al.
patent: 5196722 (1993-03-01), Bergendahl et al.
patent: 5235544 (1993-08-01), Caywood
patent: 5245570 (1993-09-01), Fazio et al.
patent: 5245572 (1993-09-01), Kosonocky et al.
patent: 5268319 (1993-12-01), Harari
patent: 5289026 (1994-02-01), Ong
patent: 5293328 (1994-03-01), Amin et al.
patent: 5297082 (1994-03-01), Lee
patent: 5301150 (1994-04-01), Sullivan et al.
patent: 5329487 (1994-07-01), Gupta et al.
patent: 5338953 (1994-08-01), Wake
patent: 5342796 (1994-08-01), Ahn et al.
patent: 5343063 (1994-08-01), Yuan et al.
patent: 5365082 (1994-11-01), Gill et al.
patent: 5371030 (1994-12-01), Bergemont
patent: 5378909 (1995-01-01), Chang et al.
patent: 5379255 (1995-01-01), Shah
patent: 5386388 (1995-01-01), Atwood et al.
patent: 5390146 (1995-02-01), Atwood et al.
patent: 5399516 (1995-03-01), Bergendahl et al.
patent: 5399917 (1995-03-01), Allen et al.
patent: 5402370 (1995-03-01), Fazio et al.
patent: 5402371 (1995-03-01), Ono
patent: 5402374 (1995-03-01), Tsuruta et al.
patent: 5406529 (1995-04-01), Asano
patent: 5408115 (1995-04-01), Chang
patent: 5424233 (1995-06-01), Yang et al.
patent: 5448094 (1995-09-01), Hsu
patent: 5453637 (1995-09-01), Fong-Chun et al.
patent: 5598037 (1997-01-01), Kikuchi et al.
Betty Prince, "Semiconductor Memories: A Handbook of Design, Manufacture, and Application", pp. 182-187, 586-608.
Seiichi Aritome et al., "Reliability Issues of Flash Memory Cells", Proceedings of the IEEE, vol. 81, No. 5, May 1993, pp. 776-788.
Shin-ichi Kobayashi et al., "Memory Array Architecture and Decoding Scheme for 3 V Only Sector Erasable DINOR Flash Memory", IEEE Journal of Solid-State Circuits, vol. 29, No. 4, Apr. 1994, pp. 454-460.
S. Wolf & R.N. Tauber, "Silicon Processing For the VLSI EVA", vol. I, pp. 384-385, 1986.
S. Wolf, "Silicon Processing For the VLSI EVA", vol. II, pp. 104-107, 32-43, 354-359.

Affiliated with

Also associated with

Rating

Three-dimensional complementary field effect transistor process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Three-dimensional complementary field effect transistor process , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Three-dimensional complementary field effect transistor process will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1323965