Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1997-10-01
2001-06-26
Beausoliel, Jr., Robert W. (Department: 2785)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S043000, C710S120000, C710S108000, C710S108000, C709S241000, C709S239000
Reexamination Certificate
active
06253334
ABSTRACT:
RELATED APPLICATION
The subject matter of U.S. Application entitled “Means For Allowing Two Or More Network Interface Controller Cards To Appear As One Card To An Operating System,” filed on Oct. 1, 1997, application Ser. No. 08/943,379, and is related to this application.
Appendices
Appendix A, which forms a part of this disclosure, is a list of commonly owned copending U.S. Patent applications. Each one of the applications listed in Appendix A is hereby incorporated herein in its entirety by reference thereto.
Appendix B, which forms part of this disclosure, is a copy of the U.S. provisional patent application filed May 13, 1997, entitled “Three Bus Server Architecture With A Legacy PCI Bus and Mirrored I/O PCI Buses,” and assigned application Ser. No. 60/046,490.
Copyright Authorization
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a system for enhancing the performance of a a computational server connected to both data storage devices and networks, and more particularly to a system that provides load balancing and fault tolerance capabilities.
2. Related Art
Personal computers (PCs) have undergone evolutionary changes since the original models based on the Intel 8088 microprocessor, such as the International Business Machine Corporation (IBM) PC and other IBM-compatible machines. As the popularity of PCs have grown, so has the demand for more advanced features and increased capability, reliability and speed. Higher order microprocessors such as the Intel 20286, 30386, 40486, and more recently, the Pentium® series have been developed. The speed of the fastest of these processors, the Pentium® II series is 266 MHz as opposed to the 8 MHz clock speed for the 8088 microprocessor.
Faster bus architectures have been developed to support the higher processor speeds. Modern computer systems typically include one or more processors coupled through a system bus to main memory. The system bus also typically couples to a high bandwidth expansion bus, such as the Peripheral Component Interconnect (PCI) bus which operates at 33 or 66 MHz. High speed devices such as small computer systems interface (SCSI) adapters, network interface cards (NIC), video adapters, etc. can be coupled to a PCI bus. An older type low bandwidth bus such as the Industry Standard Architecture (ISA), also referred to as the AT bus, is generally coupled to the system bus as well. This bus operates at 6 MHz. To the ISA bus are attached various low speed devices such as keyboard, monitor, Basic Input/Output System (BIOS) and parallel and communications ports. These devices are known as legacy devices because they trace their lineage, their legacy, back to the initial PC architecture introduced by IBM in 1982:
With the enhanced processor and bus speeds the PC now is utilized to perform as a server, and to provide high speed data transfers between, for example, a network and a storage device. There are, however, several constraints inherent in the current PC architecture, which limit its performance as a server. First, the legacy devices and the high speed devices compete for limited bus bandwidth, and thereby degrade system performance. Second, whereas the original PC operated as a standalone and did not affect other PCs when there was a system failure, the PC/Server must be able to maintain operation despite failure of individual components. The PC/Server must, in other words, be fault-tolerant, i.e. able to maintain operation despite the failure of individual components.
What is needed is a way to move the PC from a standalone model to a server model. In doing so, the inherant conflict of high and low bandwidth buses must be resolved, fault-tolerance must be provided, and throughput should be enhanced.
SUMMARY
An embodiment of the present invention provides a fault-tolerant computer system with a processor and a memory, connected to a system bus. The system includes at least two mirrored circuits, at least two mirrored input/output devices, a detection means and a re-route means. The two mirrored circuits each include an interface to the system bus, and an input/output interface. The input/output interface of each of the mirrored circuits is connected to one of the two mirrored input/output devices. Detection means detect a load imbalance in the data transfer between the system bus and either one of the two mirrored IO devices. In response the re-route means, re-routes the data transfer between the system bus and the other one of the two mirrored IO devices.
In another embodiment, a fault-tolerant computer system includes a first, second and third input/output (IO) bus, legacy devices, and two IO devices. The first IO bus is connected to the system bus. The legacy devices are connected to the first IO bus. The second and third IO buses are each connected to the system bus. The IO devices are each connected to a corresponding one of the second and third IO buses.
An other embodiment of the invention can be characterized as an apparatus for transferring data between at least one transport protocol stack and a plurality of network adapters coupled to a computer network that supports recovery from network adapter and a connection failure. The apparatus includes a first interface bound to at least one transport protocol stack and a plurality of network adapters coupled to a computer network that supports recovery from network adapter and connection failure. The apparatus includes a first interface bound to at least one transport protocol stack. It also includes a second interface bound to the plurality of network adapters, as well as a mechanism coupled to the first interface and the second interface that receives a first MAC-level packet from a transport protocol stack through the first interface and forwards the first MAC-level packet through the second interface to a network adapter in a protocol independent matter. The apparatus also includes a mechanism coupled to the first interface and the second interface that receives the second packet from a network adapter through the second interface and forwards the second packet through the first interface to a transport protocol stack.
According to another aspect of the present invention, the apparatus can function as a prescan protocol stack for examining packets flowing between protocol stacks and drivers.
REFERENCES:
patent: 4057847 (1977-11-01), Lowell et al.
patent: 4100597 (1978-07-01), Fleming et al.
patent: 4449182 (1984-05-01), Rubinson et al.
patent: 4672535 (1987-06-01), Katzman et al.
patent: 4692918 (1987-09-01), Elliott et al.
patent: 4695946 (1987-09-01), Andreasen et al.
patent: 4707803 (1987-11-01), Anthony, Jr. et al.
patent: 4769764 (1988-09-01), Levanon
patent: 4774502 (1988-09-01), Kimura
patent: 4821180 (1989-04-01), Gerety et al.
patent: 4835737 (1989-05-01), Herrig et al.
patent: 4894792 (1990-01-01), Mitchell et al.
patent: 4949245 (1990-08-01), Martin et al.
patent: 4968977 (1990-11-01), Chinnaswamy et al.
patent: 4999787 (1991-03-01), McNally et al.
patent: 5006961 (1991-04-01), Monico
patent: 5007431 (1991-04-01), Donehoo, III
patent: 5033048 (1991-07-01), Pierce et al.
patent: 5051720 (1991-09-01), Kittirutsunetorn
patent: 5073932 (1991-12-01), Yossifor et al.
patent: 5103391 (1992-04-01), Barrett
patent: 5118970 (1992-06-01), Olson et al.
patent: 5121500 (1992-06-01), Arlington et al.
patent: 5123017 (1992-06-01), Simpkins et al.
patent: 5136708 (1992-08-01), Lapourtre et al.
patent: 5136715 (1992-08-01), Hirose et al.
patent: 5138619 (1992-08-01), Fasang et al.
patent: 5157663 (1992-10-01), Major et al.
patent: 5210855 (1993-05-01), Bartol
patent: 5245615 (1993-09-01), Treu
patent: 5247683 (1993-09-01), Holmes et al.
patent: 5253348 (199
Agneta Don A.
Amdahl Carlton G.
Smith Dennis H.
Baderman Scott T.
Beausoliel, Jr. Robert W.
Knobbe Martens Olson & Bear LLP
Micron Electronics Inc.
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