Electrical computers and digital processing systems: virtual mac – Task management or control – Process scheduling
Reexamination Certificate
2005-02-11
2009-12-08
Zhen, Li B (Department: 2194)
Electrical computers and digital processing systems: virtual mac
Task management or control
Process scheduling
C718S103000, C718S104000
Reexamination Certificate
active
07631308
ABSTRACT:
A method is disclosed in a data processing system for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors that concurrently execute multiple threads during each clock cycle. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles. The clock cycle priority is assigned according to a standard selection definition during the standard selection state by selecting the first thread to be a primary thread and the second thread to be a secondary thread during the standard selection state. If a condition exists that requires overriding the standard selection definition, an override state is executed during which the standard selection definition is overridden by selecting the second thread to be the primary thread and the first thread to be the secondary thread.
REFERENCES:
patent: 6269391 (2001-07-01), Gillespie
patent: 2006/0136915 (2006-06-01), Aingaran et al.
patent: 2006/0168254 (2006-07-01), Norton et al.
Bishop James Wilson
Le Hung Qui
Nguyen Dung Quoc
Sinharoy Balaram
Thompto Brian William
Gerhardt Diana R.
International Business Machines - Corporation
Yee & Associates P.C.
Zhen Li B
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