Thin, thermally enhanced flip chip in a leaded molded package

Details Thin, thermally enhanced flip chip in a leaded molded package Thin, thermally enhanced flip chip in a leaded molded package

2007-12-20

2010-10-26

Williams, Alexander O (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Insulating material

C257SE23044, C257SE23051, C257SE23046, C257SE23039, C257SE23052, C257SE23047, C257SE23124, C257SE23040, C257SE23101, C257SE23023, C257SE23037, C257SE23034, C257SE25029, C257SE27060, C257S684000, C257S692000, C257S666000, C257S696000, C257S676000, C257S778000, C257S690000, C257S288000, C257S728000, C257S328000, C257S687000, C257S775000, C257S698000, C257S673000, C257S315000, C257S276000

Reexamination Certificate

active

07821124

ABSTRACT:
Semiconductor die packages and methods of making them are disclosed. An exemplary package comprises a leadframe having a source lead and a gate lead, and a semiconductor die coupled to the source and gate leads at a first surface of the leadframe. The source lead has a protruding region at a second surface of the leadframe. A molding material is disposed around the semiconductor die, the gate lead, and the source lead such that a surface of the die and a surface of the protruding region are left exposed by the molding material. An exemplary method comprises obtaining the semiconductor die and leadframe, and forming a molding material around at least a portion of the leadframe and die such that a surface of the protruding region is exposed through the molding material.

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