Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2002-05-23
2003-11-25
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S221000, C438S296000, C438S359000, C438S424000, C438S778000
Reexamination Certificate
active
06653203
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the fabrication of integrated circuits and, more specifically, to the use of a novel high-density plasma (HDP) method for filling gaps and trenches in integrated circuit structures which is particularly effective when said gaps and trenches have stepped cross-sectional profiles that would prevent void free and damage free filling by the usual methods.
2. Description of the Related Art
Many processes in the fabrication of integrated circuits require the formation of variously shaped trenches in the substrate and their subsequent filling, using sputtering and plasma enhanced deposition processes. For example, the fabrication of DRAM circuits requires dielectric filled trenches for the formation of storage capacitors. There are also a wide variety of circuit topologies (including DRAM circuits) that require portions of the circuit to be isolated from each other by shallow trenches (“shallow trench isolation” or STI). As circuits progressively shrink in size, the aspect ratio (depth/width) of these trenches become larger as their widths become appreciably smaller than their depths (widths with outside diameters <0.2 microns being common) and a subsequent complete and uniform filling is rendered problematic due to the angular distribution of the sputtered dielectric atomic species in the deposition process. In particular, such atoms tend to follow a line of sight trajectory, causing poor coverage on steeply slanted trench sidewalls. A particularly serious problem that results is the production of fills having internal voids. Compounding the problem of void formation is the fact that the trenches are often formed in multilayered substrates, such as silicon substrates on which there are successive layers of silicon oxides and silicon nitrides. It is not uncommon that the upper nitride layer is pulled back from the edge of the trench by amounts between 100-500 angstroms to reduce gate oxide thinning when the nitride layer is subsequently removed. This nitride pull-back produces a stepped cross-sectional profile in the trench, leading to a shadowing and overhang effect as the dielectric fill material is deposited within the trench. Another cause of voids during the filling process is a re-deposition effect associated with the use of argon as a sputtering gas.
The various problems associated with trench filling and methods of eliminating or reducing them have been noted in the prior art. Jang et al. (U.S. Pat. No. 6,037,018) teaches a method for filling shallow trenches (STI) with a high density plasma chemical vapor deposition (HPDCVD) oxide. The method so taught has a primary objective of protecting the trench sidewalls from the effects of the sputtering process by first depositing an O
3
-TEOS barrier layer. The method, however, does not specifically address the problem of void formation. Andideh et al. (U.S. Pat. No. 5,270,264) teach a method for filling gaps between metal lines on integrated circuits by means of interlayer dielectric (ILD) deposition using plasma enhanced chemical vapor deposition (PECVD). The method involves three steps, (1) CVD ILD deposition, (2)medium pressure argon sputter etch and (3) CVD ILD deposition. Wu et al. (U.S. Pat. No. 6,150,238) teach a method of filling isolation trenches wherein voids are intentionally formed in a sequence of successive depositions and then removed by etching. Their method primarily addresses trench filling using less costly atmospheric pressure chemical vapor deposition (APCVD), using ozone and TEOS as the reactive gases. Yao et al. (U.S. Pat. No. 6,048,775) teach a method for planarizing a non-conformally deposited HDPCVD oxide trench fill that is deposited over a pad oxide and a nitride layer. The oxide is deposited at a deposition to sputter ratio (D/S ratio) between 2.5:1 and 7:1. The method so taught is primarily concerned with the planarization of trench fills, particularly the elimination of “dishing” problems associated with chemical mechanical polishing. Lin (U.S. Pat. No. 5,920,792) teaches a method for depositing and planarizing dual HDP-CVD layers on integrated microelectronsics circuits. The layers are deposited using combined deposition and etch processes wherein the etching gas component is argon and the deposition component gas is silane. The HDP-CVD layers taught by Lin also provide a superior trench filling capability. Narwankar et al. (U.S. Pat. No. 6,200,911 B1) teaches a method for modifying the profile of narrow, high aspect ratio gaps on a semiconductor substrate so as to allow their filling in a void-free manner. The method taught by Narwankar involves differential heating of the top and bottom surfaces of the substrate, using an argon plasma for preheating purposes and by carefully controlling top and side coil plasma chamber power. Silane and argon were the gases utilized in this process. Papasouliotis et al (U.S. Pat. No. 6,030,881) teach a method for filling high aspect ratio gaps (>5:1) without the formation of voids. Specifically, the method encompasses a sequence of HDP deposition and etch steps having varying etch-to-deposition rate ratios, wherein the first step uses a rapid deposition in a gas mixture comprising oxygen, silane and argon or helium (an inert gas). This deposition is halted before voids are formed, following which there is applied a step with a more rapid etch rate so as to open up the entry to the partially filled trench. Thereupon, a sequence of deposition and etch steps are applied until the aspect ratio of the increasingly filled trench is low enough to allow a complete fill with a deposition step.
The method of Papasouliotis et al. is not directed at stepped-profile trench openings on substrates in which an upper nitride layer is pulled back from a lower gate oxide layer to reduce the gate oxide thinning. Such stepped-profile openings, while advantageous, present considerable problems in trench filling as the step exacerbates the formation of overhangs. In addition, the method of Papasouliotis et al teaches the use of an inert gas in the initial deposition step, whereas the present inventors have determined that the use of such a gas in the initial step will create nitride damage and enhance void formation by the process of redeposition. Further, the present invention uses a first process step in which there is a high deposition to sputtering ratio and a second step in which there is a low deposition to sputtering ratio, unlike the method taught by Papasouliotis, in which the first and second depositions are the same. It is in an effort to address the void formation problems associated with stepped-profile trench openings and redeposition as well as to reduce the damage to the nitride layer caused by the etching process that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of this invention is to provide a method for filling trenches in integrated circuits.
A second object of the present invention is to provide a method for filling trenches having a high aspect ratio without the resulting formation of voids within the filling material.
A third object of the present invention is to provide a method for filling high aspect ratio trenches having a stepped cross-sectional profile such as would be caused by the formation of said trenches in a substrate on which a nitride layer overlays an underlying oxide layer and wherein said nitride layer has been pulled back from the oxide layer at the trench opening.
A fourth object of the present invention is to provide a method for filling such high aspect ratio trenches in a substrate covered by an oxide and a nitride layer in a manner that avoids a redeposition effect and eliminates damage to the nitride layer, said damage causing problems for endpoint detection during the subsequent chemical mechanical polishing.
In accord with the objects of this invention there is provided a method for filling high aspect ratio trenches, and particularly such trenches formed in substrates in which a nitride layer overlays an oxide l
Huang Tsung-Hsun
Tu Yeur-Luen
Yu Chung Yi
Ackerman Stephen B.
Jr. Carl Whitehead
Pham Thanhha
Saile George O.
Taiwan Semiconductor Manufacturing Company
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