Thin oxide dummy tiling as charge protection

Details Thin oxide dummy tiling as charge protection Thin oxide dummy tiling as charge protection

2011-07-12

2011-07-12

Landau, Matthew C (Department: 2813)

Semiconductor device manufacturing: process

Formation of semiconductive active region on any substrate

Polycrystalline semiconductor

C438S283000, C438S287000, C438S296000, C438S591000, C257SE21660, C257SE21678, C257SE21683

Reexamination Certificate

active

07977218

ABSTRACT:
Novel fabrication methods implement the use of dummy tiles to avoid the effects of in-line charging, ESD events, and such charge effects in the formation of a memory device region region. One method involves forming at least a portion of a memory core array upon a semiconductor substrate that involves forming STI structures in the substrate substantially surrounding a memory device region region within the array. An oxide layer is formed over the substrate in the memory device region region and over the STI's, wherein an inner section of the oxide layer formed over the memory device region region is thicker than an outer section of the oxide layer formed over the STI's. A first polysilicon layer is then formed over the inner and outer sections comprising one or more dummy tiles formed over one or more outer sections and electrically connected to at least one inner section.

REFERENCES:
patent: 5668035 (1997-09-01), Fang et al.
patent: 5885856 (1999-03-01), Gilbert et al.
patent: 5998264 (1999-12-01), Wu
patent: 6157067 (2000-12-01), Hsu et al.
patent: 6211016 (2001-04-01), Wu
patent: 6255169 (2001-07-01), Li et al.
patent: 6277723 (2001-08-01), Shih et al.
patent: 6383861 (2002-05-01), Gonzalez et al.
patent: 6432726 (2002-08-01), Iranmanesh
patent: 6569723 (2003-05-01), Liaw
patent: 6645801 (2003-11-01), Ramsbey et al.
patent: 6797565 (2004-09-01), Yang et al.
patent: 6867956 (2005-03-01), Clark et al.
patent: 6897110 (2005-05-01), He et al.
patent: 6905967 (2005-06-01), Tian et al.
patent: 7030012 (2006-04-01), Divakaruni et al.
patent: 7033900 (2006-04-01), Rekhi et al.
patent: 7120063 (2006-10-01), Liu et al.
patent: 7410857 (2008-08-01), Higashi et al.
patent: 2002/0041526 (2002-04-01), Sugita et al.
patent: 2002/0048192 (2002-04-01), Wang et al.
patent: 2003/0098479 (2003-05-01), Murthy et al.
patent: 2003/0132475 (2003-07-01), Kanamori
patent: 2004/0120198 (2004-06-01), Schwalbe et al.
patent: 2004/0259298 (2004-12-01), Graf et al.
patent: 2005/0191808 (2005-09-01), Steimle et al.
patent: 2006/0063364 (2006-03-01), Stephens et al.
patent: 2006/0086953 (2006-04-01), Lee et al.
patent: 2006/0231910 (2006-10-01), Hsieh et al.
patent: 2007/0070673 (2007-03-01), Borkar et al.
patent: 2007/0077713 (2007-04-01), Ha et al.
patent: 2008/0265309 (2008-10-01), Higashi et al.
patent: 2009/0154214 (2009-06-01), Sugimae et al.

Affiliated with

Also associated with

Rating

Thin oxide dummy tiling as charge protection does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Thin oxide dummy tiling as charge protection, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Thin oxide dummy tiling as charge protection will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2677821