Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2001-04-30
2004-02-17
Fourson, George (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S773000, C257S774000, C257S775000, C148S033200
Reexamination Certificate
active
06693342
ABSTRACT:
TECHNICAL FIELD
This invention relates to thin microelectronic substrates and methods for manufacturing and processing such microelectronic substrates.
BACKGROUND OF THE INVENTION
Packaged microelectronic assemblies, such as memory chips and microprocessor chips, typically include a microelectronic substrate die encased in a plastic, ceramic or metal protective covering. The die includes functional devices, such as memory cells, processor circuits, and interconnecting circuitry. The die also typically includes bond pads electrically coupled to the functional devices. The bond pads are coupled to pins or other types of terminals that extend outside the protective covering for connecting to buses, circuits and/or other microelectronic assemblies.
Conventional microelectronic assemblies are typically mounted on a circuit board or other support device that is incorporated into a computer, mobile phone or other larger electronic product. One drawback with this arrangement is that the packaged microelectronic assemblies can extend a substantial distance away from the surface of the circuit board. Accordingly, it may be difficult to fit the circuit board and the attached microelectronic assemblies into the housing of a compact, low profile electronic product.
One approach to address this problem is to reduce the thickness of the packaged microelectronic assembly by reducing the thickness of the die within the package. For example, in one conventional arrangement, the functional features of the die are formed on or proximate to one surface of a substrate wafer. After forming these features, the opposite surface of the wafer is ground down (“backgrinding”) by chemical-mechanical planarization (“CMP”) or other techniques to reduce the overall thickness of the wafer. The wafer is then placed on an adhesive film and cut or singulated to form individual dies. The adhesive film is stretched to separate adjacent dies from each other and a suction cup removes the singulated dies from the adhesive film. The singulated dies are then encapsulated in the protective covering to form a packaged die having a reduced thickness.
One drawback with the backgrinding approach is that the amount of material that can be removed from the wafer by this process is limited because the wafer must remain sturdy enough to withstand the stresses applied to the wafer during the backgrinding process and other subsequent steps, such as transporting the wafer, mounting the wafer to the adhesive film and cutting the wafer. For example, the conventional techniques known by the inventors for reducing the thickness of the die typically cannot produce wafers less than about 150 microns thick without causing an unacceptable increase in the number of broken or damaged wafers and/or dies.
SUMMARY OF THE INVENTION
The present invention is directed toward microelectronic substrates and methods for processing microelectronic substrates. A method in accordance with one aspect of the invention includes providing a substrate having a first surface and a second surface facing a direction opposite from the first surface. The method further includes forming a plurality of voids in the first surface with each void extending to a separation region beneath the first surface. At least one operable microelectronic device is formed at and/or proximate to the first surface of the substrate. The method still further includes separating a first stratum of the microelectronic substrate above the separation region from a second stratum of the microelectronic substrate below the separation region.
In a further aspect of the invention, the method can further include at least partially filling the voids with a filler material to close an open end of the voids at the first surface of the substrate, constructing a film on the first surface of the substrate, and forming at least one microelectronic device in the film. The voids can be filled with tungsten and can have a tapered shape with a larger open area at the separation region than at the first surface of the substrate.
The invention is also directed toward a microelectronic die. In one embodiment, the die includes a substrate having a first external surface, a second external surface facing a direction opposite from the first external surface, and a plurality of operable microelectronic devices at and/or proximate to at least one of the external surfaces. A thickness of the substrate between the first and second external surfaces is less than about 150 microns. In another aspect of the invention, the second external surface has a plurality of voids extending from the second external surface toward an intermediate location between the first and second external surfaces.
The invention is also directed toward a process for forming microelectronic susbstrates and a product formed by the process. In one embodiment, the process includes providing a substrate material with a first surface and a second surface facing a direction opposite from the first surface, forming a plurality of voids in the first surface with each void extending to a separation region between the first and second surfaces, and forming at least one operable microelectronic device at or proximate to the first surface of the substrate. The method can further include separating a first portion of the microelectronic substrate above the separation region from a second portion of the microelectronic substrate below the separation region.
REFERENCES:
patent: 5107328 (1992-04-01), Kinsman
patent: 5138434 (1992-08-01), Wood et al.
patent: 5374564 (1994-12-01), Bruel
patent: 5494835 (1996-02-01), Bruel
patent: 5496755 (1996-03-01), Bayraktaroglu
patent: 5696002 (1997-12-01), Frank et al.
patent: 5773352 (1998-06-01), Hamajima
patent: 5938956 (1999-08-01), Hembree et al.
patent: 5946584 (1999-08-01), Ishikiriyama
patent: 6066514 (2000-05-01), King et al.
patent: 6089920 (2000-07-01), Farnworth et al.
patent: 6096574 (2000-08-01), Smith
patent: 6097091 (2000-08-01), Ohsumi
patent: 6110825 (2000-08-01), Mastromatteo et al.
patent: 6114221 (2000-09-01), Tonti et al.
patent: 6225651 (2001-05-01), Billon
patent: 6259153 (2001-07-01), Corisis
patent: 6294837 (2001-09-01), Akram et al.
patent: 6300670 (2001-10-01), Kramer et al.
patent: 6303469 (2001-10-01), Larson et al.
patent: 6319751 (2001-11-01), Lin
Wolf and Tauber; Silicon Processing for the VLSI Era vol. 1: Process Technology; pp. 27, 30-31; Lattice Press 1986: Sunset Beach, California.
Ellis Mark W.
Larson Charles E.
Long Jon M.
Murphy Timothy E.
Riley Vincent L.
Fourson George
Toledo Fernando
LandOfFree
Thin microelectronic substrates and methods of manufacture does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Thin microelectronic substrates and methods of manufacture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Thin microelectronic substrates and methods of manufacture will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3316287