Thin metal barrier for electrical interconnections

Details Thin metal barrier for electrical interconnections Thin metal barrier for electrical interconnections

1997-07-18

2001-09-18

Quach, T. N. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S761000, C257S762000, C257S768000

Reexamination Certificate

active

06291885

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to metal interconnects and more particularly to a metal diffusion barrier and liner for VLSI and ULSI metal interconnects, studs, for CMOS gate stacks on semiconductor chips, and for electrical interconnections in packaging and display devices.
BACKGROUND OF THE INVENTION
On VLSI and ULSI semiconductor chips, Al and alloys of Al are used for conventional chip wiring material. The incorporation of Cu and alloys of Cu as a chip wiring material results in improved chip performance and superior reliability when compared to Al and alloys of Al. However, Cu must be successfully isolated from the devices formed in the silicon substrate below and from the surrounding back end of the line (BEOL) insulators. To accomplish this isolation i.e. to prevent diffusion of Cu, a thin liner material is deposited on the patterned BEOL insulator, e.g. trenches formed in the Damascene process, or unpatterned insulator e.g. Cu reactive ion etching (RIE) or through mask Cu deposition process before the Cu is deposited. The thin film liner must also serve as adhesion layer to adhere the copper to the surrounding dielectric. Adhesion of copper directly to most insulators is generally poor.
TiN has been evaluated as a Cu barrier and has been reported in the literature as a barrier for Cu interconnects in SiO
2
. In a publication by S-Q Wang, MRS Bulletin 19, 30, (1994) entitled “Barriers against copper diffusion into silicon and drift through silicon dioxide”, various barrier systems including TiN are shown for placement between Si/SiO
2
and Cu. TiN has good adhesion to SiO
2
. However, Cu adheres poorly to TiN. A very thin glue or adhesion layer of Ti may be used to enhance the adhesion of Cu to TiN; however, this Ti layer drastically degrades the conductivity of the copper film during subsequent thermal processing. In addition, TiN has been known to form a corrosion couple with copper in certain copper polishing slurries used in chemical mechanical polishing (CMP).
Unlike TiN, pure or oxygen-doped Ta adheres poorly to some insulators such as SiO
2
. It also forms the high-resistivity beta-phase Ta when deposited directly on the insulator. Furthermore, the Cu barrier properties of Ta fail when it is in contact with Al at moderate temperatures. See for example, the publication by C. -K Hu et al., Proc. VLSI Multilevel Interconn. Conf. 181, (1986) which described an investigation of diffusion barriers to Cu wherein tantalum, silicon nitride and titanium nitride were found to be the good diffusion barriers to Cu. It is reported that oxygen in the Ta films may have inhibited Cu diffusion.
In a publication by L. A. Clevenger et al., J. Appl. Phys. 73, 300 (1993), the effects of deposition pressure, in situ oxygen dosing at the Cu/Ta interface, hydrogen and oxygen contamination and microstructure on diffusion barrier failure temperatures for HV and UHV electron-beam deposited Ta thin films penetrated by Cu were investigated.
Ta
2
N has been proposed as a good copper diffusion barrier, but its adhesion to BEOL insulators and copper is relatively poor. In contrast, the adhesion of TaN (N
18
50%) is adequate, while the adhesion of Cu to TaN is poor. A thin Ta layer can be used to enhance the adhesion of Cu to TaN, without the Ta degrading the performance of Cu BEOL. Such a dual-component liner has been previously disclosed in U.S. Pat. No. 5,281,485 Jan. 25, 1994 to E. G. Colgan and P. M. Fryer. However, the resistivity of this Ta(N) is at least 1200 Micro Ohm-cm, which leads to larger vias or stud resistances, and the inability of the metal liner to act as a redundant current strap or path.
For deep-submicron vias (e.g. less than 0.5 um wide) with
~
250 Å liner at the bottom, the series resistance of the above Ta-based liners is in the range from 1 to 5 Ohms. By contrast, the copper stud resistance would be less than 10% of the Ta based liner. Although these via resistances compare very favorably with those of Al(Cu)/W-stud values, it is desirable to reduce them below the 1 Ohm range.
SUMMARY OF THE INVENTION
In accordance with the present invention, a barrier layer is provided comprising a layer of TaN in the hexagonal phase positioned between a first material to be confined and a second material whereby the second material is isolated from said first material. The first material may be one or a combination of Cu, Al, W and PbSn.
The invention further provides a layer of TaN in the hexagonal phase which may be positioned between the gas WF6 and a second material to be isolated from the first material.
The invention further provides an interconnect structure comprising a first insulation layer having an upper and lower surface and having a plurality of grooves formed in the upper surface, some of the grooves having regions extending to the lower surface to expose respective conducting surfaces in a second interconnect structure below the first insulation layer, a liner including a layer of TaN in the hexagonal phase formed on the sidewalls and bottom of the plurality of grooves and on the exposed respective conducting surfaces, and a metal formed in the plurality of grooves to substantially fill the plurality of grooves.
The invention further provides a liner or barrier layer for VLSI/ULSI interconnects and C4 solder bumps made mostly of Pb—Sn which simultaneously achieves good diffusion barrier performance, good adhesion to BEOL insulators, good adhesion of interconnect metal to this liner, low resistivity, and good conformality in trenches and vias. The interconnects and studs may comprise aluminum, copper, tungsten, or C4 solder balls made of lead-tin alloy.
The invention provides a liner composed of predominately highly oriented and non-highly oriented (random) hexagonal phase TaN (30-60% nitrogen) (which may contain up to 50% cubic phase TaN) deposited alone or as a thin film laminate in combination with other suitable metal films such as Ta. Preferably, the TaN is 100% hexagonal phase.
The liner material described above provides a high integrity barrier, low stress, low resistivity and excellent adhesion to both metal and various dielectrics, such as polymers, silicon dioxide, BPSG, and diamond-like carbon and isolates lead-tin solder metallurgy from Cu and Al interconnects.
The invention further provides a thin film material for isolating Al wiring levels from an immediate Cu interconnection level above or below.
The invention further provides a liner which isolates a metal layer of W, Cu, alloys of Cu, Al and alloys of Al from the contact silicide (WSi
21
, CoSi
2
, TiSi
2
, TaSi
2
and PtSi) and polycrystalline silicon in a MOSFET (metal oxide semiconductor field effect transistor) gate stack.
The invention further provides a liner to shield existing metal from certain gases such as WF
6
, which is corrosive and used as a precursor gas for the deposition of W.
The invention further provides a liner which provides good contact resistance to preceding levels of metal, such as aluminum in BEOL wiring.
The invention further provides a liner which provides markedly better conformality than Ti-based compounds even without collimation sputtering or chemical vapor deposition (CVD).
The invention further provides a thin film to isolate BEOL interconnect metals from alloying or mixing with the lead-tin in for example, C4 solder balls.
The invention further provides a liner material exhibiting good conformality when deposited in trenches and vias of BEOL structures.
The invention further provides a liner material which will not form a corrosion couple with Cu, Al, or W during or after chemical mechanical polishing of the liner material.


REFERENCES:
patent: 4385116 (1983-05-01), Nair et al.
patent: 4789648 (1988-12-01), Chow et al.
patent: 4944836 (1990-07-01), Beyer et al.
patent: 5221449 (1993-06-01), Colgan et al.
patent: 5281485 (1994-01-01), Colgan et al.
patent: 5316974 (1994-05-01), Crank
patent: 0 024 863 A3 (1981-03-01), None
patent: 0 568 108 A1 (1993-03-01), None
patent: WO 92/07968 (1992-05-01), None
CRC Handbook of Chem. and Physics, Ed., 197

Affiliated with

Also associated with

Rating

Thin metal barrier for electrical interconnections does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Thin metal barrier for electrical interconnections, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Thin metal barrier for electrical interconnections will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2475974