Thin film transistors for liquid crystal displays

Details Thin film transistors for liquid crystal displays Thin film transistors for liquid crystal displays

1998-06-05

2001-08-14

Prenty, Mark V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Amorphous semiconductor material

C257S059000

Reexamination Certificate

active

06274884

ABSTRACT:

BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to thin film transistors for liquid crystal displays.
(b) Description of the Related Art
Recently, liquid crystal displays (LCDs) using amorphous silicon thin film transistors (hereinafter “TFTs”) as switching elements are widely used in notebook personal computers and car navigation systems.
However, photo leakage currents due to the light incident on the amorphous silicon are generated in the thin film transistors, which deteriorate the characteristics of the liquid crystal displays.
A thin film transistor to reduce the photo leakage current is disclosed in U.S. Pat. No. 4,990,981 (Tanaka et al.).
However, the photo leakage currents generated in the amorphous silicon layer may not be considerably reduced in the TFT of Tanaka et al., since the amorphous silicon layer is not completely shielded by the gate electrode from the incident light from the lower side of the substrate.
Furthermore, the gate electrodes and the source/drain electrodes of Tanaka et al. may be easily shorted, since portions of the gate electrodes and the source/drain electrodes overlap via only a single insulating layer. In particular, the insulating layer may be open near the edge of the gate electrode, thereby causing the short between the gate electrodes and the source/drain electrodes.
In the meantime, because the kick-back voltage due to the parasitic capacitances between the gate electrodes and the drain electrodes cause flicker and afterimage etc., it is necessary to reduce the parasitic capacitance.
SUMMARY OF THE INVENTION
It is an object of the present invention to reduce photo leakage currents.
It is another object to reduce the parasitic capacitance between a gate electrode and a drain electrode.
It is another object to prevent the short-circuit between a gate electrode and source and drain electrodes.
A TFT according to the present invention has a gate electrode, an insulator covering the gate electrode, an amorphous silicon layer formed on the insulator, a source electrode which is formed on the amorphous silicon layer and overlaps the gate electrode, and a drain electrode which is formed on the amorphous silicon layer and opposite and separated from the source electrode, and overlaps the gate electrode. Here, the edges of the amorphous silicon layer are substantially encompassed by edges of the gate electrode and the edges of the amorphous silicon layer are spaced apart from the edges of the gate electrode by at least 2 microns.
More desirably, considering a process margin of about 1.5 microns, the edges of the amorphous silicon layer are substantially encompassed by edges of the gate electrode 3.5 microns.
Accordingly. the light obliquely incident on the amorphous silicon layer from the outside as well as the light normally incident on the amorphous silicon layer is blocked by the gate electrode.
It is desirable to add an insulation layers between the gate electrode and the source/drain electrodes to reinforce the insulation between the gate electrode and the source/drain electrodes and to absorb the light reflected by the source/drain electrodes and the gate electrode.
The insulation layers are separated from the amorphous silicon layer made of an amorphous silicon, and interposed between the edges of the source/drain electrodes and the gate electrode.
The source electrode may surround the drain electrode in annular shape, which is symmetrical with respect to a drain electrode to reduce the parasitic capacitance generated between the gate electrode and the drain electrode.
The amorphous silicon layer may extend out the gate electrode near the edges of the gate electrode which encompasses a source electrode and a drain electrode to reinforce the insulation between the gate electrode and the source/drain electrodes, without the insulation layers.
Furthermore, the source electrode may be curved to prolong the distance between the drain electrode and the portion of the amorphous silicon layer, in which the electrons and holes are generated, to minimize the photo currents.


REFERENCES:
patent: 4990981 (1991-02-01), Tanaka et al.
patent: 5049952 (1991-09-01), Choi
patent: 5055899 (1991-10-01), Wakai et al.
patent: 5877512 (1999-03-01), Kim
patent: 5883437 (1999-03-01), Maruyama et al.

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