Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-11-02
2001-11-27
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S059000, C257S282000, C257S283000, C257S284000, C257S285000
Reexamination Certificate
active
06323521
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a thin film transistor (“TFT”) and a method for fabricating the same and, more particularly, to a TFT and a method for fabricating the same in which the resistance of the source and the drain is reduced.
2. Discussion of Prior Art
A Liquid Crystal Display (“LCD”) has a plurality of pixel cells which include a switching device as a driving element and a pixel electrode as its basic units which are arranged in a matrix pattern. The switching device is a TFT including a gate region, a source region and a drain region.
TFTs are classified as top gate type TFTs in which a gate electrode is formed over an active region and bottom gate type TFTs in which a gate electrode is formed below an active region according to the relative position of the active region and the gate.
FIG. 1
is a cross-sectional view of a bottom gate type TFT of a conventional device.
A gate electrode
13
consisting of a conductive material, such as Al is formed on an insulating substrate
11
. A gate insulating layer
15
consisting of an insulating material, such as silicon oxide or silicon nitride is formed on the substrate
11
so as to cover the gate electrode
13
. An active layer
17
consisting of amorphous silicon is formed on the gate insulating layer
15
over the gate electrode
13
. An ohmic contact layer
19
consisting of heavily-impurity-doped-amorphous silicon is formed on the active layer
17
so as not to overlap the gate electrode
13
.
A source electrode
21
and a drain electrode
22
are formed on the ohmic contact layer
19
. The source and drain electrodes
21
and
22
are formed by a refractory metal material, such as Cr or Ta. A passivation layer
23
consisting of an insulating material, such as silicon oxide or silicon nitride is formed on the entire surface of the resultant structure. A contact hole
25
is formed in the passivation layer
23
to expose a portion of the drain electrode
22
. A pixel electrode
27
is formed on the passivation layer
23
and is electrically connected to the exposed drain electrode
22
. The pixel electrode
27
is formed by a transparent material, such as Indium Tin Oxide (“ITO”).
FIG. 2
is a cross-sectional view of a top gate type TFT according to a conventional device.
An active layer
33
consisting of amorphous silicon is formed on an insulating substrate
31
. A gate insulating layer
35
and a gate electrode
37
are formed sequentially on the active layer
33
. A source region
41
and a drain region
42
are formed in the active layer
33
. The source and drain regions
41
and
42
are heavily doped by N-type impurities or P-type impurities.
An insulating interlayer
35
consisting of an insulating material, such as silicon oxide or silicon nitride is formed on the entire surface of the resultant structure. First contact holes are formed in the insulating interlayer
35
to expose a portion of the source region
41
and a portion of the drain region
42
. A source electrode
44
connected to the exposed source region
41
and a drain electrode
45
connected to the exposed drain region
42
are formed on the insulating interlayer
35
. The source and drain electrodes
44
and
45
are formed from a refractory metal material, such as Cr or Ta.
A passivation layer
47
consisting of an insulating material, such as silicon oxide is formed on the insulating interlayer
39
covering the source and drain regions
41
and
42
. A second hole
49
is formed in the passivation layer
47
to expose a portion of the drain electrode
45
. A pixel electrode
51
is formed on the passivation layer
47
and electrically connected to the exposed drain electrode
45
. The pixel electrode
51
is formed of a transparent material, such as ITO.
As described above, the source and drain electrodes are formed by a refractory metal material, such as Cr or Ta in the bottom gate type TFT and the top gate type TFT according to the prior art devices. When forming the source and drain electrodes using a refractory metal material, such as Cr or Ta, the contact spiking generated in the contact surface of the amorphous silicon layer and the hillock generated in the surface may be prevented.
However, the refractory metal material makes the resistance of the switching device increase, thereby causing a reduction in the switching speed.
SUMMARY OF THE INVENTION
To overcome the problems described above, preferred embodiments of the present invention provide a TFT and a method for fabricating the same that prevent any reduction in switching speed of the TFT by forming the source and the drain electrodes to have significantly low electrical resistance while preventing deterioration of the step coverage by forming the source electrode and the drain electrode to have a double step difference.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, at least one preferred embodiment of the present invention provides a TFT including a substrate, a gate electrode on the substrate, a gate insulating layer on the substrate and covering the gate electrode, an active layer on the gate insulating layer, an ohmic contact layer on the active layer and not overlapping the gate electrode, and a source electrode and a drain electrode connected to the ohmic contact layer, each of the source electrode and the drain electrode having a double-layered structure of a first metal layer having a tensile stress and a second metal layer having a compressive stress.
In another preferred embodiment of the present invention, a TFT includes a substrate, an active layer on the substrate, a gate insulating layer on the active layer, a gate electrode on the gate insulating layer, a source region and a drain region in both sides of the active layer, an insulating interlayer on the substrate and covering the active layer and the gate electrode, first contact holes formed in the insulating interlayer and exposing the source and drain regions, and a source electrode connected to the source region and a drain electrode connected to the drain region, each of the source electrode and drain electrode having a double-layered structure of a first metal layer having tensile stress and a second metal layer having compressive stress.
In another preferred embodiment of the present invention, a method for fabricating a TFT includes the steps of providing a substrate, forming a gate electrode on the substrate, forming a gate insulating layer on the substrate such that the gate insulating layer covers the gate electrode, forming an active layer and an ohmic contact layer on the gate insulating layer, the ohmic contact layer being disposed on the active layer, and forming a source electrode and a drain electrode so as to be connected to the ohmic contact layer, each of the source electrode and the drain electrode having a double-layered structure of a first metal layer having tensile stress and a second metal layer having compressive stress.
In another preferred embodiment of the present invention, a method for fabricating a TFT includes the steps of providing a substrate, forming an active layer on the substrate, forming a gate insulating layer and a gate electrode on the active layer, the gate electrode being formed on the gate insulating layer, forming a source region and a drain region on both sides of the active layer, forming an insulating interlayer on the substrate, the insulating interlayer covering the active layer and the gate electrode, forming first contact holes in the insulating interlayer such that the first contact holes expose the source and drain
Abraham Fetsum
Birch & Stewart Kolasch & Birch, LLP
LG LCD Inc.
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