Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1999-05-27
2001-04-17
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S149000, C438S151000, C257S059000, C257S066000, C257S072000
Reexamination Certificate
active
06218221
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of making a thin film transistor (TFT) for a liquid crystal display (LCD), and more specifically, to a method of forming a TFT with a multi-metal structure as source and drain electrodes.
BACKGROUND OF THE INVENTION
There are various kind of flat panel display devices characterized by low power consumption and small size. Those devices include the liquid crystal display (LCD), plasma display panel (PDP) and electroluminescence display (ELD). The LCD has been used in electron devices successfully because of its capability for high resolution. At present, the portable computer or personal data assistant (PDA) are widely used in the mass market and those are remarkably progressing. In order to meet the requirement of portable apparatus, the displays for portable use are light weight and low power consumption. Thin film transistor-liquid crystal display (TFT-LCD) is one of the devices that can fit the aforementioned requirements and is known as the display required for the high pixel density and quality.
In general, the TFT-LCD includes a bottom plate formed with thin film transistors and pixel electrodes and a top plate formed with color filters. The liquid crystal is filled between the top plate and the bottom plate. In each unit pixel, the TFT serves as a switching element of the unit pixel. When the data voltage is applied to the TFT, the arrangement of the liquid crystal molecules is changed, thereby changing the optical properties and displaying the image. The color filter (CF) plate is used in the LCD to show the colored portion of the screen.
In the art, two types of the TFT structure are developed. One is the so called ES (etching stopper) TFT and the other one is the BCE (bask channel etched) TFT. In the type of BCE TFT, there is no etching block on the channel region, therefore, the channel region will be etched during the process because of the etching rates of the amorphous silicon and the doped silicon are similar. Please refer to
FIG. 2
, a gate electrode
22
is formed on the substrate
20
. An insulating layer
24
is next formed on the gate electrode
22
. An amorphous silicon layer
26
having a channel loss region
26
a
is over the insulating layer
24
. The amorphous layer
26
has a doped silicon layer
28
formed on a portion of the amorphous silicon layer
26
for forming ohmic contact. Source and drain (S/D) electrodes consisting of a Cr
29
a
sub-layer and an Al sub-layer
29
b
are patterned on the doped silicon layer
28
. The disadvantage of the BCE type structure is that the channel region will lose thickness during the etching for forming the S/D electrodes. In addition, the wet etching to etch the double metal (Al/Cr) layers generates undercut portions
29
c
under the Al sub-layer
29
b
due to the etching rate of the two sub-layers is different and the solution will laterally etch the Cr layer. It is hard to control the etching conditions to prevent the channel from being etched and forming the undercut portions
29
c.
Referring to
FIG. 3
, in the type of the ES TFT structure, an etching stop layer is formed over an amorphous silicon layer to prevent the channel region formed in the amorphous silicon layer from being etched while an etch is performed to form the source and drain. The ES type is shown in
FIG. 3
, the structure includes a substrate
32
, a gate electrode
34
is formed on the substrate. An insulating layer
36
is formed on the gate electrode
34
for isolation. An amorphous silicon layer
38
is patterned on the isolation layer
36
. Reference number
42
is the aforementioned etching stopper
42
to protect the channel region. Thus, it has high resistant to etch. Source and drain (S/D) electrodes
44
are formed on the amorphous silicon layer
38
and a portion of the etching stopper
42
. Typically, the S/D electrodes
44
are consisted of multi-metal layers, which are n+ doped silicon layer
44
a
, a first titanium layer
44
b
, an aluminum layer
44
c
and a further titanium layer
44
d
. The n+ doped silicon layer
44
a
is used to form ohmic contact layer. In the structure, a portion of the ES layer
42
is exposed by the S/D electrodes
44
. The channel region under the ES layer
42
will not be attacked during the etching to form S/D electrodes
44
. However, the channel length of the ES type TFT is longer than BCE type TFT structure.
As the display resolution is going higher and higher, the performance of the TFT is also pushed higher and higher. From the device performance point of view, the BCE type TFT has the advantage of shorter channel length. Considering the channel loss, wet etch of the S/D metal is preferred. However, a multi-layer structure is usually applied for the source and drain metal. As shown in
FIG. 1
, a triple-layer
4
consists of a first barrier metal
4
a
, a major conducting layer
4
b
(usually Al) and a second barrier metal
4
c
, such as a Mo/Al/Mo structure. In order to obtain a taper etching profile, the etching rate of the metal layer
4
a
must be higher than that of Al. Because
4
c
is usually similar to
4
a
, it is easy to form an Al overhang structure as shown in
FIG. 1
, which is not a healthy profile. Furthermore, the channel length is determined by the CD of the layer
4
c
, which is the CD defined by the photoresist plus the side etch of the Al and layer
4
c
. As a result, the BCE TFT performance is strongly degraded.
Thus, what is required is a novel method to form the TFT to avoid aforementioned disadvantages of BCE and ES TFT.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a method of forming a TFT by using a multi-metal S/D structure.
A second object of the present invention is to form a TFT by using two steps of etching including a dry etching and a wet etching to pattern the S/D metal.
A third object of the present invention is to prevent the critical dimensions (CD) loss issue and to reduce the channel region loss problem.
A forth object of the present invention is to form a contact structure between S/D and thereafter formed transparent conducting layer via a via hole in the passivation layer which is formed between said S/D structure and thereafter formed transparent conducting layer.
The present invention includes providing an insulating transparent substrate. A gate such as metal or alloy is patterned on the transparent substrate. Next, a gate isolation layer is formed on the gate electrode for isolation. The gate isolation is composed of silicon oxide or silicon nitride. A semiconductor layer such as amorphous silicon (a-Si) layer is subsequently formed on the gate isolation layer. A n+ doped silicon layer is formed on the upper surface of the a-Si layer. The n+ doped layer can be created by implanting ions into the upper surface of the a-Si layer or by forming a doped silicon layer directly by using plasma chemical vapor deposition (CVD). Then, the a-Si layer and the n+ doped silicon layer are patterned by means of lithography technique.
A first, a second and a third metal layers are successively formed on the n+ doped silicon layer, thereby forming a multi-metal layer structure. The upper metal layer (the third metal layer) is selected from Mo, MoN. The second metal layer is formed by aluminum or aluminum alloy, such as AlNd. The lower metal layer is selected from the group of Cr (chromium), Ti (titanium), Cr alloy, Ti alloy and titanium nitride. A wet etching is used to etch the third metal layer and the second metal layer. Preferably, the etching rate of the third metal layer is higher than that of the second metal layer (aluminum).
Subsequently, a dry etching is utilized to etch the first metal layer and the n+ doped layer, thereby defining the S/D electrodes. Residual n+ doped silicon layer covered by the first metal layer will remain on a portion of the amorphous silicon to act as an ohmic contact layer.
Thereafter, a passivation layer is deposited on the whole surface. Then, patterning is applied to the passivation laye
Chi Mei Optoelectronics Corp.
Le Dung A
Nelms David
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