Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2002-10-11
2004-11-16
Nguyen, Cuong (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S764000, C438S585000
Reexamination Certificate
active
06818485
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a thin film transistor, a method of producing the thin film transistor, a thin film transistor array substrate using the thin film transistor, and display devices using the thin film transistor array substrate such as a liquid crystal display device and an electroluminescent display device. More particularly, the invention relates to a thin film transistor having a channel region, a source region, and a drain region, the source and drain regions having a low melting point region composed of a semiconductor having a melting point lower than that of the semiconductor in the channel region, and relates to fabrication methods and applications of the thin film transistor.
(2) Description of the Prior Art
The escalating demands for increased performance in electronic appliances employing thin film transistors (hereafter, also abbreviated as TFTs) require further scaling down of the sizes, higher response speed, and lower power consumption in the TFTs. The requirements are particularly strong in TFTs for use in display devices, such as active matrix driven liquid crystal display devices. In order to meet these requirements, it is necessary that a thin film transistor having a channel region with a short channel length and a short channel width be driven at low voltage.
Conventionally, the channel region, the source region, and the drain region in a thin film transistor are formed of the same kind of semiconductor. Amorphous silicon thin film transistors (a-Si TFTs) and polycrystalline silicon thin film transistors (p-Si TFTs), in which those regions are formed of amorphous silicon thin film and polycrystalline silicon thin film, respectively, are well known in the art. In addition, polycrystalline silicon germanium thin film transistors (p-SiGe TFT) have been disclosed in Japanese Unexamined Patent Publication Nos. 6-61489 and 6-120499.
To date, a-Si TFTs and p-Si TFTs have been widely used in display devices such as liquid crystal display devices and electroluminescent display devices (hereafter abbreviated as EL display devices). In addition, there is a prior-art technique for liquid crystal display devices and EL display devices in which, using p-Si TFTs, pixel TFTs and peripheral driver circuit TFTs are both formed on a glass substrate.
Where the channel region, the source region, and the drain region are made of the same kind of semiconductor, the dopant leaks and diffuses into the channel region during the heat treatment for activating a dopant contained in the source region and the drain region in the fabrication, reducing the effective channel region and degrading the performance of the TFT. Furthermore, in the cases of p-Si TFTs and p-SiGe TFTs, the dopant likewise leaks and diffuses into the channel region when a crystallization step is performed after the doping of the dopant.
In the case of a p-Si TFT, due to the fact that, in polycrystalline silicon, the dopant diffuses fast along the grain boundaries, the dopant contained in the source region and the drain region leaks and diffuses even more widely into the channel region. Further, in the case of a TFT in which a polycrystalline silicon thin film is used for the channel region, the OFF current is larger than that of a TFT in which an amorphous silicon thin film is used for the channel region. In order to control the OFF current, there are prior art techniques which involve the forming of a lightly doped drain (LDD) region, in which the dopant concentration is low, or the forming of a source region having a low dopant concentration and a drain region having a low dopant concentration.
In a TFT having an LDD region and a channel region composed of a polycrystalline silicon thin film, the LDD region, which is in contact with the channel region, has a low dopant concentration, and therefore, the amount of dopant that diffuses into the channel region is small. However, the resistance rate of a polycrystalline silicon thin film having a low dopant concentration is easily affected by the dopant concentration, and therefore, even if the amount of diffused dopant is small, the resistance value greatly varies, causing the additional problem of it being difficult to form an LDD region exhibiting a uniform concentration. In other words, in the TFT, a uniform parasitic resistance is difficult to obtain, and a large variation in the driving current is caused. This discussion is also applicable to a source region having a low dopant concentration.
In the case of p-SiGe TFTs, according to Japanese Unexamined Patent Publication Nos. 6-61489 and 6-120499, the temperature of the heat treatment during the fabrication can be reduced, and thereby the leaking and diffusing of the dopant into the channel region is reduced. However, as with the case where the channel region is formed of a polycrystalline silicon thin film, the OFF current increases. Moreover, in the case where polycrystalline silicon germanium is used for the channel region, the density of the crystal defect increases when compared to that in the case where polycrystalline silicon is used for the channel region, degrading the subthreshold characteristics.
Furthermore, where reduction of the sizes of a-Si TFTs, p-Si TFTs, and p-SiGe TFTs is necessary, the dopant diffusion more acutely affects the degradation of TFT characteristics since the width of the diffusion of the dopant into the channel region is invariable. Therefore, the proportion of the diffusion resistances of the source and drain regions to the parasitic resistance of the TFT increases, degrading the driving performance of the TFT. In addition, where it is necessary to ensure a certain channel length in the channel region in which the dopant is not diffused, the source region and the drain region must be made smaller. However, if the contact areas between the source region and the source electrode and between the drain region and the drain electrode are made smaller, the proportion of the contact resistance to the parasitic resistance increases.
In summary, the prior art TFT has the following problems. 1) When the channel region, the source region, and the drain region are formed of the same kind of semiconductor, the dopant concentration in a boundary portion of the source region adjacent to the channel region and that in a boundary portion of the drain region adjacent to the channel region are difficult to precisely control. 2) In particular, in application fields requiring high-speed driving characteristics such as in display devices, the channel region needs to be formed of a polycrystalline semiconductor, but the use of polycrystalline semiconductor for the channel region necessitates reduction in off-current by providing an LDD region. Therefore, if the dopant concentration cannot be precisely controlled, it is difficult to uniformly form TFTs having unvarying characteristics. 3) When a polycrystalline silicon germanium thin film is used for the channel region, it is possible to reduce the temperature of the heat treatment required in the fabrication process, but the subthreshold characteristics of the TFT tend to degrade.
SUMMARY OF THE INVENTION
In view of the foregoing and other problems of the prior art, it is an object of the invention to provide a TFT having a channel region composed of a first semiconductor, a source region comprising a first low melting point region composed of a second semiconductor having a melting point lower than that of the first semiconductor, and a drain region comprising a second low melting point region composed of a third semiconductor having a melting point lower than that of the first semiconductor, whereby the dopant concentrations of a first dopant contained in the boundary portion of the source region adjacent to the channel region and of a second dopant contained in the boundary portion of the drain region adjacent to the channel region are precisely controlled. It is a second object of the invention to provide a method of producing the TFT of the invention. It is a third object of
Nguyen Cuong
Parkhurst & Wendel L.L.P.
LandOfFree
Thin film transistor, thin film transistor array substrate,... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Thin film transistor, thin film transistor array substrate,..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Thin film transistor, thin film transistor array substrate,... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3354114