Thin film transistor substrate with testing circuit

Details Thin film transistor substrate with testing circuit Thin film transistor substrate with testing circuit

1999-09-30

2001-06-12

Ngô, Ngân V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

C257S059000, C257S072000, C257S350000

Reexamination Certificate

active

06246074

ABSTRACT:

This application claims the benefit of Korean Patent Application Nos. P98-41209 and P98-48785, filed on Sep. 30 and Nov. 13, 1998, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a thin film transistor (TFT) matrix substrate having TFTs arranged in a matrix pattern, and more particularly to a TFT matrix substrate having a testing circuit for testing the TFT matrix.
2. Description of the Related Art
Generally, a TFT matrix substrate has TFTs formed in a rectangular shape and includes data lines and gate lines. Each data line connects drain electrodes of the TFTs and each gate line connects gate electrodes of the TFTs to each other. Each of the TFTs connected between the gate lines and the data lines responds to a scanning signal from the gate line to switch a data signal to be applied to a pixel cell, such as a liquid crystal cell. The gate lines for applying the scanning signal to the TFTs and the data lines for applying the data signal may get disconnected or break due to a manufacturing tolerance of the TFT matrix substrate, a working error, and so on. If the gate line is broken or disconnected, then the TFTs connected to the gate line can not be driven. On the other hand, if the data line is broken or disconnected, then a data signal is not applied to a part of TFTs. In order to check if the gate line or the data line has a break, the TFT matrix substrate is provided with a testing circuit.
For example, as shown in
FIG. 1
, a TFT matrix substrate having a testing circuit includes TFTs
14
arranged in each intersection between the gate line
10
and the data line
12
. The TFTs
14
apply respectively voltage signals on the data lines
12
to pixel electrodes
14
A when a high level voltage is supplied to the gate lines
10
. Odd-numbered gate lines of the gate lines
10
are commonly connected to a first test line
16
A while the remaining even-numbered gate lines of the gate lines
10
are commonly connected to a second test line
16
B. Odd-numbered data lines of the data lines
12
are commonly connected to a third test line
16
C while the remaining even-numbered data lines of the data lines
12
are commonly connected to a fourth test line
16
D. Each end of the first and second test lines
16
A and
16
B is provided with gate test pads
18
A for receiving a gate test signal. The first and second test lines
16
A and
16
B apply the gate test signal from the gate test pads
18
A to the gate lines
10
when it is intended to test if any gate lines
10
are broken down. Likewise, each end of the third and fourth test lines
16
C and
16
D is provided with data test pads
18
B for receiving a data test signal. The third and fourth test lines
16
C and
16
D apply the data test signal from the data test pads
18
B to the data lines
12
when it is intended to test if any data lines
12
have a break therein.
Further, the TFT matrix substrate includes static electricity preventing circuits or static electricity preventing patterns or devices
20
connected to each of the gate lines
10
and the data lines
12
. The static electricity preventing patterns
20
connected to the gate lines
10
are positioned at the opposite sides to the first and second test lines
16
A and
16
B and, at the same time, commonly connected to a low level gate line
22
. The static electricity preventing patterns
20
connected to the data lines
12
are positioned at the opposite sides to the third and fourth test lines
16
C and
16
D and, at the same time, commonly connected to a common voltage line
24
. Such static electricity preventing patterns
20
intercept static electricity to be transferred to the gate lines
10
or the data lines
12
, thereby protecting the TFTs
14
from the static electricity.
In the TFT matrix substrate as described above, there occurs a case where the break in the gate line
10
is not detected because of current leaks due to the static electricity preventing circuits or static electricity preventing patterns. More specifically, the static electricity preventing pattern
20
connected to the broken gate line
10
or the broken data line
12
forces a test signal voltage to be charged into the low level gate voltage line
22
or the common voltage line
24
, upon testing of the substrate. Then, the voltage charged in the low level gate voltage line
22
or the common voltage line
24
is applied to the broken gate line
10
or the broken data line
12
. As a result, the broken gate line
10
or the broken data line
24
can be normally driven. Due to this, the break in the gate line
10
and data lines
12
is not readily detected.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a TFT matrix substrate having a testing circuit that is capable of accurately detecting the breaking down of gate lines and data lines.
A further object of the present invention to provide a testing method of a TFT matrix substrate that can accurately detect the breaking down of gate lines and data lines.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
In order to achieve these and other objects of the invention, a thin film transistor matrix substrate according to an aspect of the present invention includes thin film transistors connected to gate lines and data lines at the intersection of the gate lines and the data lines, static electricity preventing means installed at each of the gate lines and the data lines, a first shorting bar connected to the gate lines commonly, a second shorting bar connected to the data lines commonly, a first test pad for receiving a first test signal to be applied to the first shorting bar, a second test pad for receiving a first test signal to be applied to the second shorting bar, a third shorting bar commonly connected to static electricity preventing means installed at the gate lines in the static electricity preventing means, a fourth shorting bar commonly connected to static electricity preventing means installed at the data lines in the static electricity preventing means, and charge preventing means for preventing a voltage from being charged into the third and fourth shorting bars when testing if the gate lines and the data lines has been broken down.
A thin film transistor matrix substrate according to another aspect of the present invention includes thin film transistors connected to gate lines and data lines forming a matrix, a first shorting bar connected to the gate lines, a second shorting bar connected to the data lines, a first test pad connected to the first shorting bar and responsive to a first test signal, a second test pad connected to the second shorting bar and responsive to the first test signal, a first set of discharge circuits connected to the gate lines, a second set of discharge circuits connected to the data lines, a third shorting bar connected to the first set of discharge circuits coupled to the gate lines, a fourth shorting bar connected to the second set of discharge circuits coupled to the data lines, and a jumper connected between the first and third shorting bars.
A testing method of the thin film transistor matrix substrate having thin film transistors connected to gate lines and data lines at the intersection of the gate lines and the data lines, static electricity preventing means installed at each of the gate lines and the data lines, a first shorting bar commonly connected to the gate lines, a second shorting bar commonly connected to the data lines, and a third shorting bar commonly connected to static electricity preventing means installed to the gate lines in the static electricity preventing means, includes the steps of applying a first test

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