Thin film transistor substrate having low resistive and chemical

Details Thin film transistor substrate having low resistive and chemical Thin film transistor substrate having low resistive and chemical

1996-12-26

1998-10-13

Niebling, John

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438 30, 438158, 438658, H01L 2184

Patent

active

058211594

ABSTRACT:
A first method of forming a thin film transistor substrate having at least an electrode interconnection, wherein a first low resistive metal layer is formed, which extends on the top surface of the substrate by sputtering method. A second low resistive metal layer is formed, which is highly resistant to chemicals and extends on the top of the first low resistive metal layer by sputtering method. A photo-resist film is applied on the second low resistive metal layer for exposure and development thereof to form a photo-resist etching mask. The first and second low resistive metal layers are subjected to an isotropic etching by use of the photo-resist etching mask. A third low resistive metal layer which is highly resistant to chemicals are formed over an entire region of the substrate by sputtering method. The third low resistive metal layer is subjected to a reactive ion etching to leave the third low resistive metal layer on the opposite sides of the first low resistive metal layer. The photo-resist mask is removed so that the first low resistive metal layer is formed without being exposed to developer, resist release solution and cleaning solution.

REFERENCES:
patent: 5472889 (1995-12-01), Kim et al.
patent: 5496752 (1996-03-01), Nasu et al.
patent: 5518936 (1996-05-01), Yamamoto et al.
patent: 5585290 (1996-12-01), Yamamoto et al.

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