Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-11-09
2003-09-23
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S061000, C257S401000, C257S408000, C257S412000
Reexamination Certificate
active
06624473
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a thin film transistor and, more particularly to the LDD type thin film transistor used in the pixel switching element of liquid crystal display and in its drive circuit, etc. and to their manufacturing method.
BACKGROUND ART
Much active in recent years have been the various researches into the liquid crystal display unit using the active matrix type display substrate provided with the thin film transistor (hereafter also referred to as “TFT”) for each pixel electrode and the EL display, which give higher picture quality than that of the non-active matrix type display. Further, researched and proposed has been so-called drive circuit incorporating liquid crystal display unit, where the TFT as pixel switching element and drive circuit are formed on the same glass substrate making use of the fact that the electron mobility of polysilicon (hereafter also referred to as “p-Si”) TFT is higher by one or two units than that of amorphous silicon (hereafter also referred to as “a-Si”) TFT.
However, in this case, there are some technical problems concealed in the nature and performance of the TFT as the semiconductor element itself used in the drive circuit or in its usage for liquid crystal display unit and the like.
Viewed from the standpoint of the nature and performance of the semiconductor element, which is rather the former problems, it should be noted that the p-Si TFT features a larger off current than that of a-Si TFT and MOS type field-effect transistor, and Japanese Provisional Publication 136417-1993 discloses and proposes a thin film transistor where a lightly doped drain (hereafter referred to as “LDD”) area is provided in the directly adjoining area of TFT source or drain source area in order to reduce the said off current.
In the simply LDD-structured TFT, however, it is possible to decrease the off current, but the lightly doped drain area, which is relatively high resistance layer, is inserted in series into the channel area when it is turned on where the channel under the gate electrode of TFT does reverse, thereby reducing the on current.
This has led to the proposition of the TFT of various LDD structures with reduced on-current. [SID96, Digest pp.25: Samsung Electronics (hereafter referred to as “the first conventional example”), Euro Display 1996 pp.555, Asia Display 1995 pp.335: Philips (hereafter referred to as “the second conventional example”).
FIG. 1
illustrates the construction of the first conventional example. In this figure, the numeral
10
represents a glass substrate. The numeral
150
is the source area (n+ layer) of the semiconductor layer consisting of p-Si, while
160
is the drain area (n+ layer) of the same. The numeral
170
represents the channel area of the same.
In this figure, the subgate electrode
41
is provided as if it covered the gate electrode
4
with the LDD areas (light doped drain area: n-layer)
151
and
161
provided on the semiconductor layer on the source and drain sides beneath the subgate electrode
41
. This construction, when it is turned off, makes the semiconductor layers
151
and
161
of the LDD area beneath the subgate electrode
41
a high resistance layer with the carrier being exhausted, and subsequently, this suppresses the off current. However, when it is turned on, the electrons that become carriers will accumulate in the LDD areas
151
and
161
, and these areas will become low resistance areas, and therefore no on-current reduction will occurs there.
In reality, these TFTs are formed over several rows and columns in horizontal and vertical directions in response to the standard, etc. of pixels, for instance, at the positions on the substrate that correspond to the drive circuits of each pixel and peripheral portion of the pixel. Through the intermediary of the interlayer dielectric the gate, source and drain electrodes constitute the multilayer interconnection mechanism. However, as these are self-evident matters, their drawings are omitted here, and any individual mentions to the similar effect are limited to the necessary least in any subsequent descriptions and drawings of embodiments.
Next,
FIG. 2
depicts the second conventional example. In this figure, the numeral
10
represents a glass substrate. The numerals
150
,
160
, and
170
respectively represent the source area (n+ layer), drain area (n+ layer), and channel area of the semiconductor layer consisting of p-Si. This figure illustrates so-called TFT of GOLD (Gate-drain Overlapped Lightly-doped Drain, gate-overlapped) structure, and more concretely, the gate electrode
4
is provided as if it hung over the LDD areas (n-layer)
152
and
162
on both sides of the channel area, that is on the source side and drain side. In this construction, as was with the first conventional example, when it is turned off, the lightly doped drain areas
152
and
162
beneath the gate electrode
4
become high resistance layer with the carrier being exhausted, and this therefore allows to suppress the off-current. If, on the other hand, it is turned on, the lightly doped drain areas
152
and
162
will become low resistance areas partly because they are beneath the gate electrode and partly because the electrons that become carrier accumulate there, and therefore, no on-current will reduce there.
However, in any process that actualizes such a TFT structure, the LDD area formed in the polycrystalline silicon semiconductor layer in order to suppress the reduction in on-current has been formed by injecting particular impurities using the ion-doping method. When injecting (or “doping”) particular impurities (different from any “impurities” in other technical fields, they are some substances positively injected into the polycrystalline silicon in order for the semiconductor element to display their function; namely, they are not any “contaminants”), any substance other than the necessary impurities, the hydrogen atoms, for instance, will be doped at the same time. And, in particular, when hydrogen is doped into the channel portion of the polycrystalline silicon just beneath the gate electrode, the hydrogen will come to intervene among the polycrystalline silicon atoms connected with each other, which causes the electrons to be trapped. This will raise the threshold value of voltage of the TFT, thereby remarkably reducing the dependability.
It is therefore indispensable for solving the assignment of the electric characteristics in the p-Si TFT to provide an infinitesimal LDD (lightly doped drain) area adjoining at least to one of TFT's source area and drain area. However, such difficulties as shown below will arise from forming these lightly doped drain area:
1) High refinement of the liquid crystal display unit requires to miniaturize the pixel transistor to heighten the display density. However, the exposure system that is normally used in the manufacture of liquid crystal display unit is mainly an equifold exposure system, which naturally limits the refinement of the pixel transistor. It is consequently very difficult to form the miniature lightly doped drain area (of the order of 0.1 to 2 or 3 &mgr;m) equivalent to or less than the channel width (approximately 1 to several &mgr;m) of the pixel transistor.
2) Since the superposition of the subgate electrode over the lightly doped drain area is made by mask overlaying, these superpositions cannot be made self-consistently (inevitably well superposed at a high accuracy when viewed from the injection direction of the impurities). The deviation in the mask overlaying causes the dimensions of the lightly doped drain area to vary, which in turn requires some margin for the mask overlaying because of the process control for manufacturing in a limited short period of time, and this restricts the refinement of the pixel TFT. In consequence, the occupancy area of the pixel TFT will increase as much as the margin is assured.
3) As the occupancy area of the pixel TFT grows larger, the parasitic capacitance between the source and drain areas incr
Ikuta Shigeo
Inoue Mayumi
Kawakita Tetsuo
Kuramasu Keizaburo
Takehashi Shin-itsu
Eckert George
Matsushita Electric - Industrial Co., Ltd.
Parkhurst & Wendel L.L.P.
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