Thin film transistor having an insulating membrane layer on a po

Details Thin film transistor having an insulating membrane layer on a po Thin film transistor having an insulating membrane layer on a po

1999-11-18

2000-08-08

Picardat, Kevin M.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

438149, 438151, H01L 2100, H01L 2184

Patent

active

061001228

ABSTRACT:
A thin film transistor and its fabrication method are disclosed wherein the thin film transistor includes a semiconductor substrate, an active layer formed on an upper surface of the semiconductor substrate, a membrane layer formed on a portion of the active layer and defining an offset region in the active layer, a gate insulation layer formed on portions of the membrane layer and the active layer, a gate electrode formed on a portion of the gate insulation layer, and a source region and a drain region formed in the active layer.

REFERENCES:
patent: 5747830 (1998-05-01), Okita
patent: 5815223 (1998-09-01), Watanabe et al.
patent: 5827755 (1998-10-01), Yonehara et al.
patent: 5925894 (1999-07-01), Yang
patent: 6011276 (2000-01-01), Yang
Tanaka, et al., "Characteristics of Offset-Structure Polycrystalline-Silicon Thin-Film Transistors," Ron Device Letters, vol. 9, No. 1 (Jan. 1988) pp. 58-60.

Affiliated with

Also associated with

Rating

Thin film transistor having an insulating membrane layer on a po does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Thin film transistor having an insulating membrane layer on a po, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Thin film transistor having an insulating membrane layer on a po will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1149394