Thin film transistor having a self-aligned gate underlying a cha

Details Thin film transistor having a self-aligned gate underlying a cha Thin film transistor having a self-aligned gate underlying a cha

1992-08-03

1993-08-10

James, Andrew

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257262, 257283, 257347, 257507, 257510, H01L 2978

Patent

active

052351890

ABSTRACT:
A self-aligned, under-gated TFT device (10). A base layer (14) is formed. A conductive layer (16) is formed overlying the base layer (14). A dielectric layer (18) is formed overlying the conductive layer (16). A sacrificial layer (20) is formed overlying the dielectric layer (18). The layers (16, 18, and 20) are etched to form a "pillar" region. A dielectric layer (22) and a planar layer (24), which both overlie the "pillar" region, are etched back to form a substantially planar surface and expose a top portion of the sacrificial layer (20). The sacrificial layer (20) is removed and a conductive layer (28) is formed overlying conductive region (16) and planar layer (22). Conductive layer (28) is used to form a self-aligned TFT device (10) via the formation of a source region (33) and a drain region (34) adjacent an aligned plug region (32).

REFERENCES:
patent: 4614021 (1987-04-01), Hulsweh
patent: 4654121 (1987-03-01), Miller et al.
patent: 4656731 (1987-04-01), Lam et al.
patent: 4803176 (1989-02-01), Bower
patent: 4876582 (1989-10-01), Janning
patent: 5028555 (1991-07-01), Haskell
patent: 5057885 (1991-10-01), Matsumoto et al.
patent: 5100817 (1987-04-01), Cederbaum et al.

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