Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-06-23
2002-03-12
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S351000
Reexamination Certificate
active
06355956
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a thin film transistor and more specifically, the present invention relates to a method for manufacturing a thin film transistor having a protective layer arranged to protect source and drain metal lines when a substrate upon which the thin film transistor undergoes a cleaning process.
2. Description of the Background Art
FIGS. 1A-1D
are cross-sectional views illustrating a process for manufacturing a thin film transistor according to the related art.
Referring to
FIG. 1A
, source and drain metal lines are formed on an insulating substrate
100
. The source metal line is defined by a double-layered laminate of a first source metal line
11
S and a second source metal line
12
S. The drain metal line is defined by a double-layered laminate of a first drain metal line
11
D and a second drain metal line
12
D. A low resistance metal such as aluminum (Al) is used to form the first and second source metal lines
11
S and
12
S. Using a low resistance metal for the source metal lines allows for faster signal transmission in a device where the thin film transistor is used, for example, in a liquid crystal display device.
Referring to
FIG. 1B
, a buffer layer and an amorphous silicon layer are sequentially deposited to cover the exposed portion of the substrate
100
. Thereafter, the amorphous silicon layer is crystallized into a polysilicon layer and then patterned and etched to form an active layer
14
. The underlying buffer layer
13
is then etched with the active layer
14
functioning as a mask.
Referring to
FIG. 1C
, a gate insulating layer and a conductive layer are sequentially deposited on the exposed portion of the substrate
100
and the active layer
14
. The conductive layer is patterned and etched to form a gate electrode
16
. Next, the gate insulating layer
15
is etched with the gate electrode
16
functioning as a mask.
Thereafter, select portions within the active layer
14
are doped with impurities to define a source region
14
S and a drain region
14
D. A channel region
14
C located between the source region
14
S and the drain region
14
D is also defined.
Note that it is necessary to clean the exposed portion of the substrate
100
before depositing a gate insulating layer
15
on the substrate
100
. The cleaning process prevents foreign substances from contaminating the interface between the gate insulating layer
15
and the active layer
14
. The cleaning process involves wet cleaning the substrate
100
with an HF solution before depositing the gate insulating layer
15
onto the substrate
100
.
Referring to
FIG. 1D
, a protective layer
17
is deposited on the entire surface of the substrate
100
including the gate electrode
16
. The protective layer
17
is then patterned and etched to form contact holes. The contact holes expose the second source metal line
12
S, the source region
14
S, the drain region
14
D, and the second drain metal line
12
D. Next, a transparent conductive layer is deposited on the exposed portion of the substrate
100
. The transparent conductive layer is also patterned and etched, and forms a first metal line
18
-
1
, which connects the second source metal line
12
S with the source region
14
S, and a second metal line
18
-
2
, which connects the second drain metal line
12
D with the drain region
14
D.
As noted previously, in the prior art, a cleaning process with an HF solution is performed on the exposed portion of the substrate
100
before the gate insulating layer
15
is deposited onto the substrate
100
. However, because the first source metal line
11
S and the first drain metal line
11
D are made from a low resistance metal such as aluminum, the source and drain metal lines are damaged by the cleaning process because of the strong etching properties of the HF cleaning solution.
SUMMARY OF THE INVENTION
To overcome the problems described above, preferred embodiments of the present invention provide a method for manufacturing a thin film transistor where a protective layer is provided to protect source and drain metal lines, which are made from a low resistance metal such as aluminum, from being damaged during a cleaning process.
According to a first preferred embodiment of the present invention, a method of manufacturing a thin film transistor includes the steps of forming source and drain metal lines on an insulating substrate, forming a first protective layer covering the source and drain metal lines, sequentially depositing a buffer layer and a semiconductor layer on the first protective layer, forming an active layer by patterning and etching the semiconductor layer, etching the buffer layer using the active layer as a mask, performing a cleaning process before depositing a gate insulating layer on an exposed entire surface of the substrate, forming a gate insulating layer and a gate electrode on the active layer, forming source and drain regions in the active layer by doping the active layer with impurities using the gate insulating layer as a mask, forming a second protective layer covering the exposed surface of the substrate including the gate electrode, forming contact holes in the first and second protective layers so that the source and drain metal lines and the source and drain regions are exposed, and forming a first metal line connecting the source metal line and the source region, and forming a second metal line connecting the drain metal line and the drain region.
According to a second preferred embodiment of the present invention, a method for manufacturing a thin film transistor includes the steps as described in the first preferred embodiment except that the source and drain regions are formed before forming the gate electrode.
Other features, elements and advantages of the present invention will be described in more detail in the following detailed description of preferred embodiments of the present invention with reference to the attached drawings.
REFERENCES:
patent: 5402254 (1995-03-01), Sasano et al.
patent: 5913113 (1999-06-01), Seo
patent: 6040589 (2000-03-01), Zhang et al.
patent: 63-316470 (1998-12-01), None
Birch & Stewart Kolasch & Birch, LLP
Chaudhuri Olik
Doan Theresa T.
LG. Philips LCD Co. Ltd.
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