Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of...
Patent
1997-04-03
1999-11-02
Niebling, John F.
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
438765, 438770, H01L 2131
Patent
active
059769890
DESCRIPTION:
BRIEF SUMMARY
FIELD OF TECHNOLOGY
The present invention relates to technology for the formation of a gate insulation film for a thin film transistor (henceforth, TFT) used as the active element of a liquid crystal display, and so on, and to a liquid crystal display.
BACKGROUND TECHNOLOGY
Regarding methods of fabrication of thin film transistors (TFT) used as the active elements in liquid crystal displays, from the viewpoint of devising the increase of surface area and the reduction of cost, low-temperature processes and the use of inexpensive glass substrates are desirable. In such a low-temperature process, it is necessary to be able to form large-grain polysilicon films that are equivalent to those of high-temperature processes, and to activate the impurities sufficiently. Further, it is important to be able to form high-quality gate insulation films having a film quality equal to or greater than thermal oxide films.
As technology for forming gate insulation films at low temperatures, there have been from the past film formation methods such as atmospheric-pressure CVD method, low-pressure CVD method, ECR-CVD method and the like. Atmospheric-pressure CVD method and low-pressure CVD method are high in productivity, but the film quality as gate insulation films is inferior. For example, there are such problems as the increase of the space charge and surface charge in silicon oxide films, the degradation of the properties of the current at on state, the degradation of the properties of the leakage current at off state, and the shift of the threshold voltage of TFTs. Also, in the ECR-CVD method, the film quality is comparatively good, but there is a problem that the productivity is markedly low, and all of the prior film formation methods do not satisfy the conditions for film formation of gate insulation films of TFT used for the active elements of liquid crystal displays.
Also, as a low-temperature process for forming silicon oxide films, other than the above-mentioned film formation methods, there is also the plasma-enhanced chemical vapor deposition method (plasma CVD method). The plasma CVD method is a film formation method whereby a film is formed by causing a discharge in a feed gas within a reaction chamber by applying a high frequency electric power between electrodes, and causing a reaction to break down the feed gas with the plasma formed thereby. Because such a film formation method has the advantages of a high deposition rate of film, a low stress applied to the substrate, a good step coverage, and the like, it has been used up to the present for the formation of interlevel insulator film of semiconductor integrated circuits. Also, as published in Sharp Giho (Sharp Technical Journal) (No. 61, April 1995), it is coming to be seen as a film formation method for forming gate insulation films of TFT as well. The conditions of the plasma CVD method examined here are that the distance between electrodes for generating the plasma is within the range of 35 mm to 65 mm, and the pressure inside the reaction chamber is in the range of 800 mtorr to 1200 mtorr, and conditions having exceeded such ranges are not suitable for forming gate insulation films of TFT. Such is suggested in Sharp Giho, and others. The properties of film formation have been evaluated within the scope of such conditions because in addition to the space charge inside a silicon oxide film occurring more easily as the distance between the electrodes is made smaller, an surface state is generated more easily on the surface of a semiconductor film in contact with the silicon oxide film. Furthermore, the properties of the current at on state and leakage current at off state of the TFT trend to be degraded due to the presence of a surface charge originating in this surface state. Further the properties have been evaluated within the scope of conditions mentioned above, because the properties of the current at on state and leakage current at off state of the TFT tend to be degraded more as the pressure inside the reaction chamber is lowered more.
Howeve
REFERENCES:
patent: 4872947 (1989-10-01), Wang et al.
patent: 5120680 (1992-06-01), Foo et al.
patent: 5426076 (1995-06-01), Moghadam
patent: 5858819 (1999-01-01), Miyasaka
Sharp Technical Journal (No. 6, Apr. 1995) Low Temperature Deposition of High Quality Silicon Dioxide Films.
Lattin Christopher
Niebling John F.
Seiko Epson Corporation
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