Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-10-22
2003-11-04
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S059000, C257S072000
Reexamination Certificate
active
06642580
ABSTRACT:
This application claims the benefit of Korean Patent Application No. 2002-0021057, filed on Apr. 17, 2002, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to thin film transistor array substrates. More particularly, this invention relates to thin film transistor array substrates, and to their manufacturing methods, having reduced data pad and data link contact resistances.
2. Description of the Related Art
A liquid crystal display (LCD) uses electric fields to control the light transmittance through a liquid crystal to produce an image. To this end, an LCD includes a liquid crystal display panel having a matrix of liquid crystal cells, and driving circuits for driving the liquid crystal cells.
In a liquid crystal display panel, gate lines and data lines are arranged in a crossing manner. Liquid crystal cells are formed in areas defined by the crossing gate and data lines. The liquid crystal display panel includes pixel electrodes and a common electrode for producing electric fields from the liquid crystal cells. Each pixel electrode is selectively connected, via source and drain electrodes of a thin film transistor that acts as a switching device, to a data line. The gate electrode of each thin film transistor is connected to a gate line. Scanning signals applied on the gate lines switch pixel voltage signals on the data lines to the pixel electrodes.
The driving circuits include a gate driver for driving the gate lines, a data driver for driving the data lines, and a common voltage generator for driving the common electrode. The gate driver sequentially applies scanning signals to the gate lines to sequentially drive the liquid crystal cells line-by-line. The data driver applies data voltage signals (also referred to as pixel voltage signals) to the data lines when a scanning signal is applied to a gate line. The common voltage generator applies a common voltage to the common electrode. Accordingly, the LCD changes alignment states of the liquid crystal between the pixel electrodes and the common electrode in response to the pixel voltage signals on the pixels to control light transmittance, thereby displaying a picture.
For instance, an LCD having a thin film transistor array substrate is shown in FIG.
1
.
FIG. 2
shows a sectional view of the thin film transistor array substrate of
FIG. 1
taken along line A-A′. As shown in those figures, the thin film transistor array substrate includes a gate line
2
and a data line
4
on a lower substrate
34
. The gate and data lines
2
and
4
cross each other. A gate insulating film
36
is disposed between the gate and data lines
2
and
4
. A thin film transistor
6
is provided at the intersection of the gate and data lines
2
and
4
. A pixel electrode
16
is provided at a liquid crystal cell area defined by the gate and data lines
2
and
4
.
The thin film transistor
6
includes a gate electrode
8
that is connected to the gate line
2
, a source electrode
10
that is connected to the data line
4
, a drain electrode
12
that is connected to the pixel electrode
16
, and an active layer
14
that overlaps the gate electrode
8
. The active layer selectively defines a channel between the source electrode
10
and the drain electrode
12
. The active layer
14
is overlapped by the data line
4
, by the source electrode
10
, and by the drain electrode
12
. An ohmic contact layer
38
for making an ohmic contact with the data line
4
, with the source electrode
10
, and with the drain electrode
12
is provided on the active layer
14
. The thin film transistor
6
allows a pixel voltage signal applied to the data line
4
to be applied to the pixel electrode
16
in response to a gate signal applied to the gate electrode
8
.
The pixel electrode
16
is electrically connected via a first contact hole
18
through a protective film
40
to the drain electrode
12
. A voltage applied to the pixel electrode
16
and the potential applied to the common electrode on an upper substrate (not shown) produce an electric field. That electric field rotates a liquid crystal between the thin film transistor array substrate and the upper substrate owing to dielectric anisotropy. This controls the light from a light source (not shown) that passes to the upper substrate.
The gate line
2
is connected, via a gate pad portion
20
, to a gate driver (not shown,), while the data line
4
is connected, via the data pad portion
28
, to the data driver (not shown). The gate pad portion
20
is comprised of a gate pad
24
that is extended from the gate line
2
, and a gate pad protection electrode
25
that is connected, via a plurality of second contact holes
26
through the gate insulating film
36
and through the protective film
40
, to the gate pad
24
. The data pad portion
28
is comprised of a data pad
30
that is extended by way of a data link
5
from the data line
4
, and of a data pad protection electrode
31
that is connected, via a plurality of third contact holes
32
through the protective film
40
, to the data pad
30
.
Hereinafter, a method of fabricating the thin film transistor substrate having the above-mentioned structure using a five-round mask process will be described in detail with reference to
FIG. 3A
to FIG.
3
E. Referring to
FIG. 3A
, gate patterns are provided on the lower substrate
34
. To do so, a gate metal layer is formed on the lower substrate
34
by a deposition technique such as sputtering. Then, the gate metal layer is patterned by photolithography using a first mask and an etching to produce the gate patterns. A gate pattern includes the gate line
2
, the gate electrode
8
, and the gate pad
24
. The gate metal is beneficially a single-layer or double-layer structure of chrome (Cr), molybdenum (Mo), or an aluminum group metal.
Referring to
FIG. 3B
, the gate insulating film
36
, the active layer
14
, and the ohmic contact layer
38
are then provided on the lower substrate
34
with the gate patterns. To do so, the gate insulating film
36
, an amorphous silicon layer, and an n
+
amorphous silicon layer are sequentially provided by deposition techniques such as plasma enhanced chemical vapor deposition (PECVD) or sputtering. Then, the n
+
amorphous silicon layer and the amorphous silicon layer are simultaneously patterned by photolithography using a second mask and an etching process. The gate insulating film
36
is beneficially comprised of an inorganic insulating material such as silicon nitride (SiN
x
) or silicon oxide (SiO
x
).
Referring to
FIG. 3C
, source/drain patterns are then formed on sthe tructure illustrated in FIG.
3
B. To do so, a source/drain metal layer is formed using a deposition technique such as sputtering. Then, the source/drain metal layer is patterned by photolithography using a third mask and an etching process to form the source/drain patterns. Each source/drain pattern includes a data line
4
, a source electrode
10
, a drain electrode
12
, and a data pad
30
. Then, the ohmic contact layer
38
between the source electrode
10
and the drain electrode
12
is removed by a dry etching. This separates the source electrode
10
and the drain electrode
12
. The source/drain metal is beneficially made from molybdenum (Mo), titanium (Ti), tantalum (Ta), a molybdenum alloy, or chrome (Cr).
Referring to
FIG. 3D
, a protective film
40
having contact holes
18
,
26
and
32
is then formed on the structure shown in FIG.
3
C. To do so, a protective film material is formed by a deposition technique such as plasma enhanced chemical vapor deposition (PECVD). The protective film material is then patterned by photolithography using a fourth mask and a dry etching process to define the first to third contact holes
18
,
26
and
32
. As shown, the first contact hole passes through the protective film
40
and through the data electrode to expose the ohmic contact layer
38
. The second contact holes
26
pass through the protective film
40
and the gate insulating film
LG.Philips LCD Co. , Ltd.
McKenna Long & Aldridge LLP
Ngo Ngan V.
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