Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-05-10
2004-11-30
Vinh, Lan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S720000, C257S059000, C257S072000
Reexamination Certificate
active
06825125
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a thin-film-transistor-array substrate, specifically to a more reliable thin-film-transistor-array substrate by preventing a short circuit between wirings or interconnects from pads to array lines extended from a thin-film-transistor, a high productivity fabrication method of the thin-film-transistor-array substrate, and a display device using the thin-film-transistor-array substrate.
BACKGROUND OF THE INVENTION
A display device such as a liquid-crystal display device or an electroluminescence display device using an inorganic or organic active material is recently widely used in view of reduction in size and weight. To drive the display device of these types, a thin-film-transistor-array substrate (hereafter referred to as TFT array substrate) is mostly used which is formed by arranging a plurality of thin-film transistors (TFTs) on an insulating substrate made of glass.
Particularly, to meet the requirement for high resolution while achieving reduction in size and weight, it is recently studied to use a structure in which an interlayer insulating film made of a polymer insulating film containing an insulating organic polymer is formed on the entire surface of a substrate including TFTs (hereafter referred to as a PFA structure), for the above TFT array substrate. The PFA structure is particularly marked in liquid-crystal displays for which characteristics such as reduction in size and improvement in brightness are required because it is possible to increase the effective area of the pixel electrode. In the case of the TFT array substrate including the PFA structure, a contact hole is formed in an interlayer insulating film to connect a lower wiring with a pixel electrode formed on the interlayer insulating film.
In the case of conventional formation of a contact hole in a TFT array substrate including the above PFA structure, independent photolithography processes are carried out to form a contact hole formed in the interlayer insulating film and to form a through-hole reached to the underlying TFT structure through the interlayer insulating film. Therefore, a TFT array substrate including the PFA structure has an advantage that the effective area of a pixel electrode is increased while it has a disadvantage that the fabrication cost is increased.
To overcome the above disadvantage, it is studied to form an interlayer insulating film by a photosensitive resin or a photosensitive polymer composition and reduce the photolithography processes using photomasks to one step. FIGS.
12
(
a
) to
12
(
c
) show a part of a conventional fabrication process for a thin-film-transistor-array substrate including a PFA structure.
As shown in FIG.
12
(
a
), in a conventional TFT array substrate fabrication process using a photosensitive resin or a photosensitive polymer composition, an interlayer insulating film
88
is formed by applying an insulating organic polymer such as a photosensitive resin or a photosensitive polymer composition on the TFT structure including a gate wiring
82
, a gate-insulating film
84
, and a passivation film
86
on an insulating substrate
80
. The interlayer insulating film
88
is patterned by photolithography. The edge of the interlayer insulating film
88
and a contact hole are formed in the interlayer insulating film
88
in accordance with the above patterning process. The conventional example shown in FIG.
12
(
a
) shows a part of the substrate including the edge of the interlayer insulating film
88
as a cross section.
Then as shown in FIG.
12
(
b
), in the conventional fabrication method, a transparent conductive film
90
for forming a pixel electrode is deposited on the structure including the interlayer insulating film
88
by chemical vapor deposition (CVD), sputtering, or vacuum evaporation. Then, to form a structure such as a pixel electrode by patterning the deposited transparent conductive film
90
, a photoresist
92
is applied onto a TFT array substrate and exposed to the radiation and developed, then the transparent conductive film
90
is etched through a proper dry etching process or wet etching process. After the transparent conductive film
90
is etched, various conductive structures including the pixel electrode
94
shown in FIG.
12
(
c
) are formed.
In the case of the PFA structure, it is necessary to increase the thickness of the interlayer insulating film
88
in order to decrease the parasitic capacity between the lower wiring layer of the interlayer insulating film
88
and the pixel electrode
94
and to completely flatten the step due to a pattern formed on the lower layer. Therefore, to fabricate the PFA structure at only one step of photolithography process, the photoresist used to etch the transparent conductive film
90
is applied so as to be thin on the interlayer insulating film
88
and so as to be thick at the portion where the edge of the interlayer insulating film
88
is formed.
If the photoresist in such condition is exposed to a radiation, the transmissive radiation dosage is low at the lower portion of the edge of the interlayer insulating film where the film thickness of the photoresist is large and then, a sufficient development contrast is not obtained. Therefore, the photoresist
92
remains around the lower portion of the edge of the interlayer insulating film
88
. A part of the transparent conductive film under the remaining photoresist is not removed by the etching. Therefore, the transparent conductive film forms a conductive structure extending along the edge of the interlayer insulating film and it causes a short circuit.
FIG. 13
is a schematic perspective view showing the transparent conductive film
90
remaining due to the above imperfect etching at the lower portion of the edge of the interlayer insulating film
88
. As shown in
FIG. 13
, if the photoresist having large difference of the thickness as mentioned above is developed under the identical condition, the photoresist is not completely removed and then a part of the transparent conductive film
90
remains at the lower portion of the edge. As a result, wiring patterns
82
formed from a gate wiring and the like to be connected to a TFT are short-circuited. This short circuit also occurs on a wiring pattern
96
formed from a source wiring or a signal wiring. It may cause the product yield to decrease and the cost to rise.
For the purpose of explanation,
FIG. 13
shows schematically the wiring patterns
82
and
96
connected to a gate wiring and a signal wiring, respectively, being adjacently. Moreover, the edge of the interlayer insulating film may occur not only at the edge of a substrate on which a wiring or an interconnect pattern is formed but also when forming a contact hole in an area in which a thin-film transistor is formed.
To overcome the above disadvantages, various studies have been performed so far. For example, in the case of the official gazette of Published Unexamined Patent Application No. 10-20339, an insulating film for preventing a short-circuit is formed between an interlayer insulating film and a conductive film for preventing a disconnecting, and it is exposed from the edge of the interlayer insulating film. In the case of the method disclosed in this application, the edge of the insulating film for preventing the short-circuit is dropped into aligning with the edge of the interlayer insulating film in the process for etching the underlying layer by only one step of photolithography with using the interlayer insulating film as a resist. Therefore, the method disclosed in this application has a disadvantage that it is impossible to form a insulating film for preventing the short-circuit while exposing the film from the interlayer insulating film. Therefore, it is impossible to properly use the method disclosed in this application for a process in which a contact hole is formed by only one step of photolithography to improve the self-alignment of the contact hole.
Moreover, the official gazette of Published Unexamined Patent Application No. 10-170951 d
Hiromasu Yasunobu
Nakasogi Teruhiro
Blecker Ira D.
Vinh Lan
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