Semiconductor device manufacturing: process – Making device or circuit responsive to nonelectrical signal
Reexamination Certificate
2000-04-07
2003-02-25
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making device or circuit responsive to nonelectrical signal
C438S046000, C438S158000, C438S149000, C438S193000, C438S949000, C438S060000
Reexamination Certificate
active
06524876
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a thin film transistor array panel and a method for manufacturing the same.
(b) Description of the Related Art
A liquid crystal display (LCD) is one of the most popular flat panel displays (FPD). The liquid crystal display has two panels having electrodes for generating electric fields and a liquid crystal layer interposed therebetween.
The transmittance of incident light is controlled by the intensity of the electric field applied to the liquid crystal layer.
In the most widely used liquid crystal display, the field-generating electrodes are provided at both of the panels, and one of the panels has switching elements such as thin film transistors.
In general, a thin film transistor array panel is manufactured by photolithography using a plurality of photomasks. Since the photolithography process is expensive, the number of the photolithography steps needs to be minimized.
In order to prevent the delay or distortion of signals applied to wires, materials having a low resistivity, such as aluminum or aluminum alloy, are generally used. However, because of the poor contact properties between aluminum or aluminum alloy and indium tin oxide (ITO), which is used as a transparent electrode in a pad portion of a liquid crystal display, the aluminum or aluminum alloy is removed to prevent the corrosion of aluminum and aluminum alloy and a different material is then inserted therebetween. Accordingly, the manufacturing process is complicated and production costs are increased.
Also, it is desirable that a data wire transmitting image signals is made of aluminum or aluminum alloy. However, since such a data wire is connected to an ITO pixel electrode, the data wire is made of material having good contact properties such as chromium and molybdenum. Unfortunately, because material such as chromium and molybdenum has a higher resistivity than aluminum or aluminum alloy, signals are often delayed or distorted in a large scale liquid crystal display.
Also, when combining a completed thin film transistor panel and a completed color filter panel in the manufacturing process, if there are conductive particles between the two panels, the pixel electrode or the data wire of the thin film transistor panel and a common electrode of the color filter panel may be shorted.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to simplify a method for manufacturing a thin film transistor array panel for a liquid crystal display.
It is another object of the present invention to provide a method for manufacturing a thin film transistor array panel for a liquid crystal display having a good contact structure.
It is still another object of the present invention to prevent the disconnection and corrosion of wires and to minimize the delay or distortion of signals in a large scale liquid crystal display.
It is still yet another object of the present invention to reduce defects of liquid crystal displays by preventing conductive particles from shorting two panels.
These and other objects are provided, according to the present invention, by forming at least two patterns through one photolithography process. A photoresist pattern has different thickness on various positions of an etch mask. Wires are formed by a conductive layer of aluminum or aluminum alloy. In this way, a layer of aluminum or aluminum alloy only on a pad portion may be removed by the photoresist pattern. A redundant line of aluminum or aluminum alloy may be laid on the layer different from the wire. A passivation layer may be formed after the wires and a pixel electrode are formed.
According to the present invention, a conductive layer of a multi-layered structure is deposited on an insulating substrate, and then patterned to form a gate wire including a gate line and a gate electrode connected to the gate line. A gate insulating layer covering the gate wire and a semiconductor layer on the gate insulating layer opposite to the gate electrode are sequentially formed. A data wire including a data line intersecting the gate line, a source electrode connected to the data line and neighboring the gate electrode, and a drain electrode separated from the source electrode and opposite to the source electrode with respect to the gate electrode is formed. Next, a passivation layer covering the data wire is formed, and a pixel electrode connected to the drain electrode is formed. At this time, the conductive layer is selectively patterned by partially exposing the lower layer located at the middle portion of its multi-layered structure.
It is desirable that the gate wire is formed through one photolithography step using a photoresist pattern having different thickness depending on positions. The photoresist pattern may have a first portion having a first thickness, a second portion having a second thickness larger than the first portion, and a third portion having a third thickness smaller than the first thickness.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention, and, together with the description, serve to explain the principle of the invention.
FIG. 1
is a layout view of a thin film transistor array panel for a liquid crystal display according to the first embodiment of the present invention.
FIG. 2
is cross-sectional view taken along lines II-II″ of FIG.
1
.
FIGS. 3A
,
6
A,
7
A, and
8
A are layout views of a thin film transistor array panel according to a first embodiment of the present invention showing manufacturing steps.
FIGS. 3B
,
4
, and
5
are cross-sectional views taken along the line IIIB-IIIB′ of FIG.
3
A.
FIG. 6B
is a cross-sectional view at the next step following
FIG. 3B
taken along the line VIB-VIB′ of FIG.
6
A.
FIG. 7B
is a cross-sectional view at the next step following
FIG. 6B
taken along the line VIIB-VIIB′ of FIG.
7
A.
FIG. 8B
is a cross-sectional view in the next step following
FIG. 7B
taken along the line VIIIB-VIIIB′ of FIG.
8
A.
FIG. 9
is a layout view of a thin film transistor array panel for a liquid crystal display according to the second embodiment of the present invention.
FIGS. 10 and 11
are cross-sectional views taken along lines X-X′ and XI-XI′ of
FIG. 9
, respectively.
FIG. 12A
is a layout view of the thin film transistor array panel according to the second embodiment of the present invention at a first manufacturing step.
FIGS. 12B and 12C
are cross-sectional views taken along the lines XIIB-XIIB′ and XIIC-XIIC′ of FIG.
12
A.
FIGS. 13A and 13B
are cross-sectional views in the next step following
FIGS. 12B and 12C
taken along the lines XIIB-XIIB′ and XIIC-XIIC′ of FIG.
12
A.
FIG. 14A
is a layout view of thin film transistor array panel in the next step following
FIGS. 13A and 13B
.
FIGS. 14B and 14C
are respectively cross-sectional views taken along the lines XIVB-XIVB′ and XIVC-XIVC′ of FIG.
14
A.
FIGS. 15A
,
16
A, and
17
A are cross-sectional views in the next step following
FIG. 14B
taken along the line XIVB-XIVB′ of FIG.
14
A.
FIGS. 15B
,
16
B, and
17
B are cross-sectional views in the next step following
FIG. 14C
taken along the line XIVC-XIVC′ of FIG.
14
A.
FIG. 18A
is a layout view of a thin film transistor array panel in the next step following
FIGS. 17A and 17B
.
FIGS. 18B and 18C
are the cross-sectional views taken along the lines XVIIIB-XVIIIB′ and XVIIIC-XVIIIC′ of
FIG. 18A
, respectively.
FIG. 19
is a layout view of a thin film transistor array panel for a liquid crystal display according to the third embodiment of the present invention.
FIGS. 20
,
21
, and
22
are the cross-sectional view taken along the lines XX-XX′, XXI-XXI′, and XXII-XXII′ of
FIG. 19
, respectively.
FIGS. 23A
,
24
A,
26
A, and
27
A are layout views of a thin film transistor array panel according to a third embodiment of the present
Baek Bum-Ki
Hong Mun-Pyo
Huh Sung-Wook
Kim Dong-Gyu
Kim Jang-Soo
Anya Igwe U.
Hae-Chan Park
McGuireWoods LLP
Samsung Electronics Co,. Ltd.
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