Thin film transistor array panel used for a liquid crystal displ

Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material

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257 57, 257 72, 349 44, 349110, 349111, H01L 31119, H01L 310224

Patent

active

060435119

ABSTRACT:
A gate insulating layer, an amorphous silicon layer, an n.sup.+ amorphous silicon layer and a metal layer are deposited in sequence after a gate line, and a gate electrode and a gate pad are formed on a substrate. The metal layer forms a data line, a source electrode, a drain electrode and a data pad on a n.sup.+ amorphous silicon layer. A patterned light shielding film and a passivation film, or a passivation film also having a function of the light shielding film are provided. The amorphous silicon layer and the gate insulating layer are etched, using the patterned light shielding film and passivation film, or the patterned passivation film also having the function of the light shielding film as the mask. Here, the gate pad, the data pad and a part of the drain electrode are exposed. A pixel electrode connected to the drain electrode, is formed and indium tin oxide (ITO) pads covering the exposed gate pad and the exposed data pad, is formed by depositing an ITO film and etching thorough the photolithography, using a fourth mask. As a result, a thin film transistor array panel used for a liquid crystal display is fabricated by only four masks.

REFERENCES:
patent: 5289016 (1994-02-01), Noguchi
patent: 5367179 (1994-11-01), Mori et al.
patent: 5483082 (1996-01-01), Takizawa et al.
patent: 5508765 (1996-04-01), Nakagawa et al.
patent: 5610737 (1997-03-01), Akiyama et al.
patent: 5621566 (1997-04-01), Fulks et al.
patent: 5648674 (1997-07-01), Weisefield et al.
U.S. application Sec. No. 08/584,070, filed Jan. 11, 1996.

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