Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1998-09-17
2004-01-27
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S151000, C438S158000, C438S161000
Reexamination Certificate
active
06682961
ABSTRACT:
BACKGROUND OF THE INVENTION
A. Field of the Invention
The present invention relates to a thin film transistor (TFT) array panel used for a liquid crystal display (LCD) and a fabricating method thereof. More particularly, the present invention relates to a method for manufacturing a TFT array panel through a photolithography process of four steps and a TFT array panel manufactured thereby.
B. Description of the Conventional Art
Generally, a liquid crystal display (LCD) includes two panels and liquid crystal material injected therebetween. Referring to
FIG. 1
, a wiring such as gate lines (not shown) and data lines (not shown), a pixel electrode
70
and a thin film transistor
70
are formed in either panel
100
of two panels. In addition, a black matrix
210
, a color filter
220
and a common electrode
240
are formed in the other panel, and an overcoat film
230
is formed between the black matrix
210
and the color filter
220
, and the common electrode
240
.
Hereinafter, a conventional thin film transistor (TFT) array panel will be explained in detail with reference to
FIGS. 2 and 3
.
FIG. 2
is a plan view illustrating a conventional TFT array panel used for a liquid crystal display (LCD) and
FIG. 3
is a cross-sectional view cut along the line III—III in FIG.
2
.
As shown in FIG.
1
and
FIG. 2
, a gate line
11
and its branch, a gate electrode
12
, are formed on a substrate
100
. The gate line
11
and the gate electrode
12
are covered with a gate insulating layer
20
. An amorphous silicon layer
30
and an n
+
amorphous silicon layer
40
are formed on the gate insulating layer
20
. A pixel electrode
70
separated from the amorphous silicon layer
30
and the n
+
amorphous silicon layer
40
is formed on the gate insulating layer
20
. A data line
51
and a source electrode
52
, as well as a drain electrode
53
, are formed thereon and the drain electrode
53
is connected to the pixel electrode
70
. They are all covered with a passivation layer
61
, except the pixel electrode
70
. A light shielding film
62
is formed over the TFT which includes the amorphous silicon layer
30
, the n
+
amorphous silicon layer
40
, the gate electrode
12
, and the source and the drain electrodes
12
and
13
. The light shielding film
62
is made in order to prevent the leakage current in the amorphous silicon layer
30
.
FIGS. 4A
to
4
G are plan views illustrating a manufacturing process of the conventional TFT array panel shown in
FIGS. 2 and 3
.
Referring to
FIG. 4A
, metal such as Cr, Al and Ta is deposited to a thickness of about 200 to 400 nm and patterned to form a gate line
11
and a gate electrode
12
through a photolithograph process using a first mask.
Referring to
FIG. 4B
, an insulating layer
20
of SiNx or SiO
2
is deposited to a thickness of about 300 to 400 nm, and an amorphous silicon layer
30
and an n
+
amorphous silicon layer
40
are deposited in sequence. The thickness of the amorphous silicon layer
30
is 200 nm and the thickness of the n
+
amorphous silicon layer
40
is 50 nm. Then, the amorphous silicon layer
30
and the n
+
amorphous silicon layer
40
are patterned in the same shape using a second mask.
Next, referring to
FIG. 4C
, an indium tin oxide (ITO) layer is deposited to a thickness of about 50 nm, and patterned to form a pixel electrode
70
through the photolithograph process using a third mask.
Referring to
FIG. 4D
, a conductive layer such as Cr, Ta or Ti is deposited to a thickness of about 150 to 300 nm, and patterned to form a data line
51
and a source and a drain electrodes
52
and
53
thorough the photolithography using a fourth mask.
Referring to
FIG. 4E
, the n
+
amorphous silicon layer
40
is etched to expose the amorphous silicon layer
30
on the gate electrode
12
using the data line
51
and a source and a drain electrodes
52
and
53
as a mask.
Referring to
FIG. 4F
, a passivation layer
61
of SiNx is deposited and patterned. The thickness of the passivation layer
61
is in the range from 200 to 400 &mgr;m, and the portion of the passivation layer
61
on the pixel electrode
70
is removed, using a fifth mask.
Referring to
FIG. 4G
, photoresist is deposited to the thickness of about 0.5 to 3 &mgr;m and patterned to form a light shielding film
62
on the TFT through the photolithography process, using a sixth mask.
As described above, six masks are required with the exception of a pad, when fabricating the conventional TFT array panel. Furthermore, more than six masks are needed when considering the pad portion. Accordingly, the conventional method has disadvantages in that the fabrication method is complex and the manufacturing cost is high.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to reduce the number of photolithography steps, thereby reducing manufacturing cost and improving the productivity.
After patterning a passivation film and a light shielding film or a passivation film also having a function of the light shielding film in the present invention, the number of mask is reduced by etching a semiconductor layer, using the patterned film as a mask.
This will be explained in detail hereinafter.
A gate line and a gate electrode are formed on a substrate, and a gate insulating layer and a semiconductor layer are deposited in sequence. A data line, a source electrode and a drain electrode are formed through a photolithography step, after depositing a metal layer. The passivation film and the light shielding -film or a passivation film of opaque material are deposited in sequence and patterned through the photolithography step. Here, the passivation film covers over the data line, the source electrode and a part of the drain electrode. A pixel electrode is formed by depositing transparent conductive material and etching the transparent conductive material through the photolithography step, after etching the semiconductor layer, using the passivation film as the mask.
In the present invention, only four masks are required when fabricating a thin film transistor (TFT) array panel with the exception of a pad. The pattern of the semiconductor layer is the same as the passivation film except a portion under the drain electrode, which is not covered with the passivation film.
To fabricate a panel with four masks including the pad, a step for etching only the gate insulating layer for exposing the pad, should be omitted. For this, it is preferable that the pattern of the gate insulating. layer should be the same as the semiconductor layer and the gate insulating layer is patterned, using the semiconductor layer as the mask. For this, the portions that the gate insulating layer should cover, that is, the gate line and the gate electrode are covered with the passivation film and the semiconductor layer, and the passivation film on the pad is etched to expose the pad when etching the passivation film.
Additional objects and advantages of the invention are set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
REFERENCES:
patent: 5279980 (1994-01-01), Hikichi et al.
patent: 5289016 (1994-02-01), Noguchi
patent: 5334859 (1994-08-01), Matsuda
patent: 5367179 (1994-11-01), Mori et al.
patent: 5483082 (1996-01-01), Takizawa et al.
patent: 5508765 (1996-04-01), Nakagawa et al.
patent: 5610737 (1997-03-01), Akiyama et al.
patent: 5621556 (1997-04-01), Fulks et al.
patent: 5648674 (1997-07-01), Wiesefield et al.
patent: 5726007 (1998-03-01), Kawahata et al.
patent: 5818551 (1998-10-01), Park
patent: 6-82830 (1994-03-01), None
patent: 6-250210 (1994-09-01), None
Brairton Scott A
Coleman W. David
Myers Bigel Sibley & Sajovec P.A.
LandOfFree
Thin film transistor array panel used for a liquid crystal... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Thin film transistor array panel used for a liquid crystal..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Thin film transistor array panel used for a liquid crystal... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3203257