Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material
Reexamination Certificate
2002-11-06
2003-11-18
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Amorphous semiconductor material
C257S072000, C257S411000, C257S640000
Reexamination Certificate
active
06649934
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a thin film transistor (TFT) panel for a liquid crystal display (LCD) and methods for manufacturing the same.
(b) Description of the Related Art
An LCD is one of the most popular flat panel displays (FPDs). The LCD has two panels having two kinds of electrodes that generate electric fields and a liquid crystal layer interposed therebetween. The transmittance of incident light is controlled by the intensity of the electric field applied to the liquid crystal layer.
The field-generating electrodes may be formed at each of the panels or at one of the panels. One of the panels having at least one kind of the electrodes has switching elements such as thin film transistors.
In general, a TFT array panel of an LCD includes a plurality of pixel electrodes and TFTs controlling the signals supplied to the pixel electrodes. The TFT array panel is manufactured by photolithography using a plurality of photomasks. Five or six photolithography steps have been required to complete a TFT array panel. Since the photolithography process costs a lot and takes much time, it is desirable to reduce the number of the photolithography steps.
One conventional method of manufacturing a TFT array panel using four photolithography steps is disclosed in the “A TFT Manufactured by 4 Masks Process with New Photolithography” (Chang Wook Han et al., Proceedings of The 18th International Display Research Conference Asia Display 98, pp. 1109-1112, 1998. 9.28-10.1).
Meanwhile, a storage capacitor for sustaining the voltage applied to a pixel is generally provided in a TFT array panel. The storage capacitor includes a storage electrode and a portion of a pixel electrode as well as a passivation layer interposed therebetween. The storage electrode is made of the same layer as a gate wire, and the portion of the pixel electrode is formed on the passivation layer. The storage electrode is covered with a gate insulating layer, a semiconductor layer and a passivation layer, and most portion of the pixel electrode is formed directly on the substrate in Han et al. Thereby, the pixel electrode should step up the triple layers of the gate insulating layer, the semiconductor layer and the passivation layer, in order to overlap the storage electrode. It may cause a disconnection of the pixel electrode near the high step-up area.
Han et al. has a problem of forming a wide region, and it is hard to make the etch depth under the grid region to be uniform, even though a wide region is formed.
U.S. Pat. Nos. 4,231,811, 5,618,643, and 4,415,262 and Japanese patent publication No. 61-181130 and etc. which disclose similar methods as Han et al. have the same problem.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to suggest new manufacturing method of thin film transistor panels.
It is another object of the present invention to simplify the manufacturing method of a TFT array panel for an LCD, thereby reducing the manufacturing costs and increasing yield.
It is another object of the present invention to prevent current leakage problems of a TFT array panel for an LCD.
These and other objects are provided, according to the present invention, by patterning a gate insulating layer pattern having a contact hole that exposes a gate pad, along with a semiconductor layer pattern and an ohmic contact layer pattern, by etching an ohmic contact layer that is not covered by the conductor pattern having dual-layered structure, a pixel electrode and a data wire, and formed thereon, and by etching the upper conductor layer of the conductor pattern that is not covered by a passivation layer.
In a manufacturing method according to the present invention, a gate wire on an insulating substrate is formed by using a first photomask. A triple layer including a gate insulating layer pattern, a semiconductor layer pattern and an ohmic contact layer pattern on the same that covers the gate wire is formed by by using a second photomask. A conductor pattern having a double-layered structure of a lower conductor layer and an upper conductor layer is formed by using a third photomask. And the ohmic contact layer pattern that is not covered with the conductor pattern is etched out. A passivation layer is formed by using a fourth photomask and the upper conductor layer of the conductor pattern which is not covered with the passivation layer is etched.
Here, the ohmic contact layer pattern may be formed of a silicide, microcrystallized silicon or doped amorphous silicon.
The gate insulating layer pattern, the semiconductor layer pattern and the ohmic contact layer pattern may have the same shapes.
In one method, a gate insulating layer and a semiconductor layer are sequentially deposited. A silicifiable metal layer is laid on the semiconductor layer to form a silicide ohmic contact layer and is removed. Then, the ohmic contact layer, the semiconductor layer and the gate insulating layer are patterned using a third mask to form an, ohmic contact layer pattern, a semiconductor layer pattern and a gate insulating layer pattern.
In another method, a gate insulating layer and a semiconductor layer are sequentially deposited and patterned using a third mask to form a semiconductor layer pattern and a gate insulating layer pattern. The silicifiable metal layer is deposited on the semiconductor layer pattern to form an ohmic contact layer pattern of silicide, and is removed. Here, the gate wire may be made of tow layers. At this time, the lower layer may be aluminum or aluminum alloy and the upper payer may be molybdenum or molybdenum alloy. The metal layer may be chromium. Also, the lower layer may be chromium, the upper payer aluminum or aluminum alloy, and the metal layer molybdenum or molybdenum alloy.
In another method, a gate insulating layer and a semiconductor layer are sequentially deposited, and a doped amorphous silicon on the semiconductor layer is deposited and microcrystalized to form an ohmic contact layer. Then, the ohmic contact layer, the semiconductor layer and the gate insulating layer are patterned by using the third mask to form the ohmic contact layer pattern, the semiconductor layer pattern and the gate insulating layer pattern.
Furthermore, the gate insulating layer pattern, the semiconductor layer pattern and the ohmic contact layer pattern may have different shapes in the step of forming the triple layers.
In this method, a gate insulating layer, a semiconductor layer and an ohmic contact layer are sequentially deposited. Then, a photoresist layer on the ohmic contact layer is coated and developed to form a photoresist layer pattern. The photoresist pattern has a first portion, a second portion thicker than the first portion and a third portion thicker than the second portion at least. Next, the ohmic contact layer, the semiconductor layer and the gate insulating layer under the first portion are patterned to form the gate insulating layer pattern, and the ohmic contact layer and the semiconductor layer under the second portion are patterned to form the ohmic contact layer pattern and the semiconductor layer pattern.
Here, the photoresist layer is exposed and developed by using the second photomask including at least a first region, a second region and a third region having different transmittance respectively and corresponding to the first portion, the second portion and the third portion respectively. It is preferable that the photoresist layer is a positive photoresist, and the transmittance of the second region is smaller than that of the first region and is larger than that of the third region.
The second photomask includes a mask substrate and at least a mask layer formed on the mask substrate. The difference of the transmittance between the second region and the third region is controlled by forming mask layers having different transmittance levels, or by adjusting the thickness of the mask layer. Furthermore, the transmittance difference of the second photomask may be controlled by forming a slit or a lattice pattern tha
Park Woon-Yong
Song Jun-Ho
McGuireWoods LLP
Nelms David
Nguyen Dao H.
Samsung Electronics Co,. Ltd.
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