Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal
Reexamination Certificate
1999-10-22
2001-07-03
Parker, Kenneth (Department: 2871)
Liquid crystal cells, elements and systems
Particular excitation of liquid crystal
Electrical excitation of liquid crystal
C349S042000, C349S046000, C349S038000, C349S039000, C349S054000, C438S030000, C257S059000
Reexamination Certificate
active
06256077
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a thin film transistor (TFT) array panel for a liquid crystal display (LCD) and a method for manufacturing the same using four photolithography steps.
(b) Description of the Related Art
An LCD is one of the most widely used flat panel displays (FPDs). The LCD includes two panels having two kinds of electrodes for generating electric fields and a liquid crystal layer interposed between the two panels. The transmittance of incident light is controlled by the intensity of the electric field applied to the liquid crystal layer.
The field-generating electrodes are provided at both or one of the panels. One of the panels has at least one of the two types of electrodes includes switching elements such as thin film transistors.
In general, a TFT (thin film transistor) array panel of an LCD includes a plurality of pixel electrodes, and TFTs controlling signals supplied to the pixel electrodes. The TFT array panel is manufactured using a photolithography process using a plurality of photomasks. Five or six photolithography steps are used in producing a TFT array panel. Since the photolithography process is expensive and takes long, it is desirable to reduce the number of the photolithography steps. Even though manufacturing methods using only four photolithography steps have been suggested, these proposed methods are not easy to implement.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a new method for manufacturing a thin film transistor array panel for a liquid crystal display using four photolithography steps.
It is another object of the present invention to reduce the leakage of current and to protect a signal line of a liquid crystal display.
These and other objects are provided, according to the present invention, by patterning a passivation layer, a gate insulating layer and a semiconductor layer in a single step, and by forming an etch protection layer on a gate line on both sides of a data line. Thus, the protection layer and the underlying semiconductor layer thereunder are etched to separate the semiconductor layer by the data line, taking advantage of the selective etching rate between the semiconductor layer and the etch protection rate.
According to the present invention, a gate wire including a gate line and gate electrodes connected to the gate line, is formed on an insulating substrate by a first photolithography process. Next, a gate insulating layer covering the gate wire, an amorphous silicon layer acting as a semiconductor layer, a doped amorphous silicon layer acting as an ohmic contact layer, and a data conductive layer are sequentially deposited on the insulating substrate. The data conductive layer and the doped amorphous silicon layer are patterned by a second photolithography process to form a data wire including a data line intersecting the gate line, a source electrode branched from the data line, and a drain electrode located opposite to the source electrode with respect to the gate electrode, an etch protection layer located on the gate line on both sides of the data line, and an underlying ohmic contact layer. A passivation layer is deposited on the data wire, the etch protection layer and the semiconductor layer, and patterned along with the semiconductor layer and the gate insulating layer by a third photolithography process to form an opening exposing the etch protection layer and a contact hole exposing the drain electrode. Subsequently, a conductive layer is deposited and patterned by a fourth photolithography process to form a pixel electrode connected to the drain electrode. Finally, a portion of the etch protection layer not covered by the passivation layer is etched, and the exposed amorphous silicon layer and the underlying doped amorphous silicon layer are removed.
REFERENCES:
patent: 5019002 (1991-05-01), Holmberg
patent: 5466620 (1995-11-01), Bang
patent: 5834328 (1998-11-01), Jang
patent: 5920083 (1999-07-01), Bae
patent: 5994155 (1999-11-01), Kim
patent: 6022753 (2000-02-01), Park et al.
patent: 6-31053 (1994-06-01), None
Howrey Simon Arnold & White , LLP
Ngo Julie
Parker Kenneth
Samsung Electronics Co,. Ltd.
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